EPM9320ALI84-10 vs EPM9320ALC84-20 Comparison
Detailed side-by-side comparison of EPM9320ALI84-10 by Intel and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALI84-10 | EPM9320ALC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| User I/O Pins | 84 | — |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 |
| Pin-to-Pin Delay (Tpd1) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| Program Memory Technology | CMOS EEPROM | — |
| Process Technology | CMOS | 0.5 µm CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) | — |
| Operating Temperature Range | -40C to +85C (Industrial) | — |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Supply Voltage | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Operating Temperature | — | [DATA_NEEDED: commercial or industrial grade] |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |
| RoHS Status | — | [DATA_NEEDED: per Altera datasheet] |