EPM9320ALI84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel
MPN: EPM9320ALI84-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $19.95 | $19,950.00 |
Drop-in alternatives for EPM9320ALI84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320ALC84-10N
β Drop-Inβ In Stock
$21.4 / Unit
View Datasheet βEPM9320ALC84-10
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9320ALC84-15
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM9320ALC84-20
β Drop-Inβ In Stock
$10.5 / Unit
View Datasheet βEPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320ALI84-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 to 12,000 |
| Macrocells | 320 |
| User I/O Pins | 84 |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Pin-to-Pin Delay (Tpd1) | 10 ns |
| Maximum Counter Frequency | 144 MHz |
| Supply Voltage (VCC) | 5.0 V |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG |
| Program Memory Technology | CMOS EEPROM |
| Process Technology | CMOS |
| Architecture | Multiple Array MatriX (MAX) |
| Operating Temperature Range | -40C to +85C (Industrial) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
EPM9320ALI84-10 Pin Configuration
| Pin 1 | I/O β General-purpose I/O pin |
| Pin 2 | I/O β General-purpose I/O pin |
| Pin 3 | I/O β General-purpose I/O pin |
| Pin 4 | I/O β General-purpose I/O pin |
| Pin 5 | I/O β General-purpose I/O pin |
| Pin 6 | I/O β General-purpose I/O pin |
| Pin 7 | I/O β General-purpose I/O pin |
| Pin 8 | I/O β General-purpose I/O pin |
| Pin 9 | I/O β General-purpose I/O pin |
| Pin 10 | I/O β General-purpose I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β General-purpose I/O pin |
| Pin 13 | I/O β General-purpose I/O pin |
| Pin 14 | I/O β General-purpose I/O pin |
| Pin 15 | I/O β General-purpose I/O pin |
| Pin 16 | I/O β General-purpose I/O pin |
| Pin 17 | I/O β General-purpose I/O pin |
| Pin 18 | I/O β General-purpose I/O pin |
| Pin 19 | I/O β General-purpose I/O pin |
| Pin 20 | I/O β General-purpose I/O pin |
| Pin 21 | I/O β General-purpose I/O pin |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β General-purpose I/O pin |
| Pin 24 | I/O β General-purpose I/O pin |
| Pin 25 | I/O β General-purpose I/O pin |
| Pin 26 | I/O β General-purpose I/O pin |
| Pin 27 | I/O β General-purpose I/O pin |
| Pin 28 | I/O β General-purpose I/O pin |
| Pin 29 | I/O β General-purpose I/O pin |
| Pin 30 | I/O β General-purpose I/O pin |
| Pin 31 | I/O β General-purpose I/O pin |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β General-purpose I/O pin |
| Pin 34 | I/O β General-purpose I/O pin |
| Pin 35 | I/O β General-purpose I/O pin |
| Pin 36 | I/O β General-purpose I/O pin |
| Pin 37 | I/O β General-purpose I/O pin |
| Pin 38 | I/O β General-purpose I/O pin |
| Pin 39 | I/O β General-purpose I/O pin |
| Pin 40 | I/O β General-purpose I/O pin |
| Pin 41 | I/O β General-purpose I/O pin |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β General-purpose I/O pin |
| Pin 44 | I/O β General-purpose I/O pin |
| Pin 45 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 46 | I/O β General-purpose I/O pin |
| Pin 47 | I/O β General-purpose I/O pin |
| Pin 48 | I/O β General-purpose I/O pin |
| Pin 49 | I/O β General-purpose I/O pin |
| Pin 50 | I/O β General-purpose I/O pin |
| Pin 51 | I/O β General-purpose I/O pin |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β General-purpose I/O pin |
| Pin 54 | I/O β General-purpose I/O pin |
| Pin 55 | I/O β General-purpose I/O pin |
| Pin 56 | I/O β General-purpose I/O pin |
| Pin 57 | I/O β General-purpose I/O pin |
| Pin 58 | I/O β General-purpose I/O pin |
| Pin 59 | I/O β General-purpose I/O pin |
| Pin 60 | I/O β General-purpose I/O pin |
| Pin 61 | I/O β General-purpose I/O pin |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β General-purpose I/O pin |
| Pin 64 | I/O β General-purpose I/O pin |
| Pin 65 | I/O β General-purpose I/O pin |
| Pin 66 | I/O β General-purpose I/O pin |
| Pin 67 | I/O β General-purpose I/O pin |
| Pin 68 | I/O β General-purpose I/O pin |
| Pin 69 | I/O β General-purpose I/O pin |
| Pin 70 | I/O β General-purpose I/O pin |
| Pin 71 | I/O β General-purpose I/O pin |
| Pin 72 | TMS β JTAG Test Mode Select (IEEE 1149.1) |
| Pin 73 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β General-purpose I/O pin |
| Pin 76 | I/O β General-purpose I/O pin |
| Pin 77 | I/O β General-purpose I/O pin |
| Pin 78 | I/O β General-purpose I/O pin |
| Pin 79 | I/O β General-purpose I/O pin |
| Pin 80 | I/O β General-purpose I/O pin |
| Pin 81 | I/O β General-purpose I/O pin |
| Pin 82 | I/O β General-purpose I/O pin |
| Pin 83 | I/O β General-purpose I/O pin |
| Pin 84 | VCC β +5.0V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ALI84-10 is suitable for 6 applications: High-Speed Bus Address Decoding, Industrial Control Logic Integration, Peripheral Glue Logic in Telecom Equipment, State Machine Controllers, Legacy PAL/GAL/22V10 Replacement, Prototype and Educational FPGA/CPLD Boards.
High-Speed Bus Address Decoding
The EPM9320ALI84-10's deterministic 10 ns pin-to-pin delay and 320 macrocells make it ideal for address decoding and chip-select generation in 32-bit microprocessor and DSP buses. According to the MAX 9000 datasheet typical application circuits, the device replaces multiple 22V10/PAL/GAL parts with a single non-volatile CPLD, eliminating boot-PROM requirements and consolidating wait-state and interrupt-acknowledge logic on the same die. The 84 user I/Os are sufficient for full 32-bit address plus 16-bit control fan-out with margin.
Recommended
Industrial Control Logic Integration
The EPM9320ALI84-10 industrial temperature range (-40C to +85C) and EEPROM non-volatile configuration suit factory-automation controllers that must boot deterministically without external memory. According to the MAX 9000 datasheet, the device's 5V I/O tolerance interfaces directly to legacy industrial logic levels, and the 84-PLCC through-hole footprint is mechanically robust for vibration-prone environments. The instant-on behavior is critical for safety interlocks that must assert within microseconds of power-up.
Recommended
Peripheral Glue Logic in Telecom Equipment
The EPM9320ALI84-10 integrates multiple discrete glue-logic functions such as FIFO flag generation, bus-width conversion, and protocol bridging in telecom line cards. According to MAX 9000 family design guides, the 144 MHz counter frequency supports clock-rate division and framing logic for E1/T1 backplanes, while the JTAG ISP allows board-level reprogramming during commissioning. The non-volatile EEPROM eliminates the boot-PROM otherwise needed by SRAM FPGAs in the same slot.
Recommended
State Machine Controllers
The EPM9320ALI84-10's 320 macrocells and predictable 10 ns timing support multi-state Moore/Mealy controllers for protocol bridges (I2C-to-SPI, UART-to-PCI) and sequencers in test equipment. According to Altera MAX 9000 application notes, the LAB-based architecture delivers uniform timing across all output transitions regardless of which macrocells fire, a critical property for protocol compliance that SRAM FPGAs cannot guarantee without careful floorplanning.
Recommended
Legacy PAL/GAL/22V10 Replacement
The EPM9320ALI84-10 directly replaces multiple discrete PAL, GAL, and 22V10 devices on legacy boards, reducing part count, power, and PCB area. According to MAX 9000 migration guides, the EEPROM-based design pattern retains the original logic equations while enabling in-system re-programming for bug fixes. The 84-PLCC footprint fits existing PLCC-84 sockets, eliminating PCB rework during the consolidation phase of legacy product refresh.
Recommended
Prototype and Educational FPGA/CPLD Boards
The EPM9320ALI84-10 is widely used in university digital-logic labs and engineering prototypes because its 5V tolerance, PLCC socket compatibility, and JTAG ISP simplify student lab setup without boot hardware. According to manufacturer reference designs, the MAX 9000 family is supported by the legacy Altera MAX+PLUS II and Quartus toolchains, both still available as free downloads, making the part a cost-effective teaching platform for combinational and sequential logic exercises.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ALI84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ALC84-10N | EPM9320ALC84-10 | EPM9320ALC84-15 | EPM9320ALC84-20 | EPM9320LC84-15 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Speed Grade (Tpd1) | 10 ns (-10) | 10 ns | 10 ns | 15 ns | 20 ns | 15 ns |
| Maximum Counter Frequency | 144 MHz | 144 MHz | 144 MHz | 125 MHz | 111 MHz | 125 MHz |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lead-Free / RoHS | Industrial (non-RoHS legacy) | Yes (lead-free, RoHS) | Yes (lead-free, RoHS) | Yes (lead-free, RoHS) | Yes (lead-free, RoHS) | Legacy non-RoHS |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | Obsolete |
Key Differentiators
- Fastest -10 speed grade in the MAX 9000 family at industrial temperature (vs EPM9320ALC84-15)
- Industrial temperature range down to -40C (vs EPM9320ALC84-10N)
- Non-volatile EEPROM configuration eliminates boot PROM (vs Equivalent SRAM FPGA in the same slot)
Design Notes
The EPM9320ALI84-10 operates from a single 5.0V VCC rail and draws ICC in the range of a few hundred mA depending on switching activity. Place a 0.1 uF decoupling capacitor as close as possible to each VCC pin (pins 84 plus any other VCC pins per datasheet) and a single 10 uF bulk capacitor at the board supply entry. The device's CMOS EEPROM core produces brief current spikes during in-system programming, so a low-ESR bulk cap is required to hold VCC within 5% during JTAG flash cycles.
The 84-PLCC package is normally used with a through-hole PLCC socket (e.g. AMP 1-822516-1 or equivalent) to ease replacement and rework. For surface-mount designs, J-lead PLCC footprints require careful pad sizing per JEDEC MS-018. Keep JTAG signals (TCK, TMS, TDI, TDO) routed as a clean daisy chain with 4.7k pull-ups on TMS and TDI to keep the boundary-scan state machine in a known reset state; missing pull-ups can cause ISP failure that mimics a dead part.
Do not assume the LI/LC/AI prefix is decorative - the LI variants are industrial temperature, the LC variants are commercial, and the AI variants are industrial with specific speed grade. Substituting an LC (commercial) into a design that requires LI (industrial) will fail at -40C. Also note that the 5.0V I/O cannot be directly wired to 3.3V logic without a level shifter, unlike MAX II/MAX V devices that support multi-voltage I/O banks.
Although the MAX architecture is known for deterministic timing, output-edge rates on the EPM9320ALI84-10 are fast enough to cause reflections on unterminated traces longer than approximately 5 cm at 144 MHz counter speeds. Source-series termination (22-33 ohm in series with each output) is recommended for high-speed clock or bus outputs, and unused I/O pins should be configured as outputs driving ground to minimize switching noise on the VCC supply.
Compliance Information
The ALI (industrial) variant is a legacy non-RoHS part per Intel/Altera part-number convention; the ALC/ALC-N commercial lead-free variants are RoHS compliant. AEC-Q100 is not applicable since automotive qualification was not performed for MAX 9000. REACH, halogen-free, and conflict-mineral status not explicitly stated in verified sources.
