EPM9320ARC208-10 vs EPM9320ARI208-10 Comparison

Detailed side-by-side comparison of EPM9320ARC208-10 by Altera and EPM9320ARI208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9320ARC208-10 EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ Last Time Buy

Specification Comparison

Parameter EPM9320ARC208-10 EPM9320ARI208-10
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Device Family MAX 9000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 —
Usable Gates 6,000 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency 144.9 MHz —
Supply Voltage 5.0 V —
Logic Blocks (LABs) 16 —
Programmability EEPROM, in-system programmable via JTAG —
JTAG Support IEEE Std. 1149.1 compliant —
Speed/Power Optimization Per-macrocell programmable, 50% power mode available —
Package RQFP-208 (Power Quad Flat Pack) —
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] -40 C to +85 C (TA)
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Programmable Type — In System Programmable (ISP)
Number of Macrocells — 320
Number of Logic Elements/Blocks — 20
Number of Gates — 6000
Number of I/O — 132
Propagation Delay tpd(1) Max — 10 ns
Maximum Counter Frequency — 144.9 MHz
Voltage Supply - Internal — 4.5 V to 5.5 V
Package / Case — 208-BFQFP Exposed Pad
Supplier Device Package — 208-RQFP
Configuration Memory — EEPROM (non-volatile)
JTAG Interface — IEEE Std. 1149.1 compliant
PCI Compliance — PCI Local Bus Specification Rev 2.2
Product Status — Obsolete
Packaging — Tray

Datasheets & Resources

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