EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
MPN: EPM9320ARC208-10 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $24.9 | $12,450.00 |
| 1,000 | $21.4 | $21,400.00 |
Drop-in alternatives for EPM9320ARC208-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320ARC208-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9320ARI208-10
β Drop-Inβ In Stock
$27.2 / Unit
View Datasheet βEPM9320ARC208-12
β Drop-Inπ Reference alternative (not in catalog)
EPM9320ALC84-10
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9320ARI208-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9320ARC208-10 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Frequency | 144.9 MHz |
| Supply Voltage | 5.0 V |
| Logic Blocks (LABs) | 16 |
| Programmability | EEPROM, in-system programmable via JTAG |
| JTAG Support | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | Per-macrocell programmable, 50% power mode available |
| Package | RQFP-208 (Power Quad Flat Pack) |
| Mounting Type | Surface Mount |
EPM9320ARC208-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (function defined by design) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | VCC β 5.0V supply |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | VCC β 5.0V supply |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | VCC β 5.0V supply |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | VCC β 5.0V supply |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | VCC β 5.0V supply |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | VCC β 5.0V supply |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | VCC β 5.0V supply |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | VCC β 5.0V supply |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | VCC β 5.0V supply |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | VCC β 5.0V supply |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | VCC β 5.0V supply |
| Pin 107 | I/O β User I/O pin |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | GND β Ground |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | VCC β 5.0V supply |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | VCC β 5.0V supply |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | GND β Ground |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | VCC β 5.0V supply |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | GND β Ground |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | VCC β 5.0V supply |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | GND β Ground |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | VCC β 5.0V supply |
| Pin 157 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 158 | TMS β JTAG Test Mode Select (IEEE 1149.1) |
| Pin 159 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | I/O β User I/O pin |
| Pin 162 | I/O β User I/O pin |
| Pin 163 | I/O β User I/O pin |
| Pin 164 | GND β Ground |
| Pin 165 | I/O β User I/O pin |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | I/O β User I/O pin |
| Pin 168 | I/O β User I/O pin |
| Pin 169 | VCC β 5.0V supply |
| Pin 170 | I/O β User I/O pin |
| Pin 171 | I/O β User I/O pin |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | I/O β User I/O pin |
| Pin 174 | GND β Ground |
| Pin 175 | I/O β User I/O pin |
| Pin 176 | I/O β User I/O pin |
| Pin 177 | I/O β User I/O pin |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | VCC β 5.0V supply |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | I/O β User I/O pin |
| Pin 182 | I/O β User I/O pin |
| Pin 183 | I/O β User I/O pin |
| Pin 184 | GND β Ground |
| Pin 185 | I/O β User I/O pin |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | I/O β User I/O pin |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | VCC β 5.0V supply |
| Pin 190 | I/O β User I/O pin |
| Pin 191 | I/O β User I/O pin |
| Pin 192 | I/O β User I/O pin |
| Pin 193 | I/O β User I/O pin |
| Pin 194 | GND β Ground |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | I/O β User I/O pin |
| Pin 197 | I/O β User I/O pin |
| Pin 198 | I/O β User I/O pin |
| Pin 199 | VCC β 5.0V supply |
| Pin 200 | I/O β User I/O pin |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | I/O β User I/O pin |
| Pin 204 | GND β Ground |
| Pin 205 | I/O β User I/O pin |
| Pin 206 | TDO β JTAG Test Data Out (IEEE 1149.1) |
| Pin 207 | I/O β User I/O pin |
| Pin 208 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ARC208-10 is suitable for 6 applications: Bus Interface Bridging and Protocol Conversion, Address Decoding and Chip-Select Generation, Industrial Control and Factory Automation, Legacy System Upgrade and ASIC Replacement, Telecommunications Infrastructure Glue Logic, Test and Measurement Equipment.
Bus Interface Bridging and Protocol Conversion
The EPM9320ARC208-10's 320 macrocells and 10 ns tPD make it ideal for bridging asynchronous processor buses between microcontrollers, DSPs, and ASICs operating at different clock domains. With 144.9 MHz fMAX, the device can reliably resolve addresses and generate chip-selects within a single clock period even at 50 MHz bus speeds, eliminating wait-state insertion. The 208-pin RQFP exposes sufficient I/O for full 32-bit address/data buses plus control signals, while EEPROM-based ISP allows field updates when bus protocols change. Designers typically use MAX+PLUS II or Quartus to compile state machines that convert between protocols such as PCI-to-ISA, VME-to-PCI, or proprietary DSP host ports.
Recommended
Address Decoding and Chip-Select Generation
The EPM9320ARC208-10 excels at generating chip-select signals for memory and peripheral banks in microprocessor systems, where its 10 ns tPD keeps decoder latency well below typical memory access times (typically 50-70 ns for SRAM, 100-200 ns for DRAM). Each macrocell can implement a sum-of-products decode term, and 320 macrocells comfortably handle 16-32 chip-select lines with overlapping address windows. The programmable speed/power feature allows non-critical decoders to drop to half-power mode, reducing overall system power. EEPROM storage means the decode map survives power cycles without boot firmware.
Recommended
Industrial Control and Factory Automation
Industrial control systems benefit from the EPM9320ARC208-10's deterministic timing, 5V I/O tolerance for legacy sensor/actuator interfaces, and JTAG-based in-system programmability for field upgrades. The 320-macrocell capacity handles multiple PWM generators, encoder counters, and safety interlock logic on a single chip. With the industrial-temp EPM9320ARI208-10 variant, the same design operates from -40C to +85C in factory environments. The non-volatile EEPROM configuration means PLC-style controllers start executing deterministic logic immediately at power-up with no boot PROM, critical for real-time control loops.
Recommended
Legacy System Upgrade and ASIC Replacement
The EPM9320ARC208-10 is a proven drop-in replacement for legacy gate arrays and bipolar PROMs in telecommunications, military, and aerospace systems designed in the 1990s and 2000s. Its 5V tolerance and 320-macrocell capacity match the logic density of typical 10K-gate ASICs. The MAX+PLUS II toolchain accepts standard TTL libraries and EDIF netlists, enabling logic re-implementation without redesigning the surrounding analog and power circuits. JTAG-based ISP eliminates the need for socketed UV-EPROM parts in the field, simplifying logistics for long-life-cycle programs.
Recommended
Telecommunications Infrastructure Glue Logic
Telecom equipment designers choose the EPM9320ARC208-10 for mid-density glue logic in line cards, baseband processing boards, and backplane controllers. The 10 ns tPD and 144.9 MHz fMAX comfortably handle 77.76 MHz ATM cell-tax logic, E1/T1 framing, and HDLC controllers. The 208-pin RQFP package provides sufficient I/O to interface with multiple ASICs, FPGAs, and network processors without multiplexing. 5V I/O compatibility avoids level-shifters when interfacing with legacy telecom ASICs designed for 5V TTL/CMOS rails.
Recommended
Test and Measurement Equipment
Test equipment such as logic analyzers, protocol exercisers, and ATE fixtures benefit from the EPM9320ARC208-10's deterministic timing and reconfigurable architecture. Engineers can implement custom stimulus generators, response comparators, and timing-reference circuits that would be impractical in discrete 74-series logic. The JTAG interface enables rapid pattern reloading between test runs, and the EEPROM storage preserves calibration personality across power cycles. The 208-pin package exposes enough I/O to drive 16-32 channels of stimulus or monitoring simultaneously.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ARC208-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ARC208-15 | EPM9320ARI208-10 | EPM9320ARC208-12 | EPM9320ALC84-10 | EPM9320ARI208-15 |
|---|---|---|---|---|---|---|
| Package | RQFP-208 | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | PLCC-84 - different | RQFP-208 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Pin-to-Pin Delay (tPD) | 10 ns | 15 ns (+50%) | 10 ns (same) | 12 ns (+20%) | 10 ns (same) | 15 ns (+50%) |
| Maximum Frequency | 144.9 MHz | [DATA_NEEDED] | 144.9 MHz | [DATA_NEEDED] | 144.9 MHz | [DATA_NEEDED] |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | Commercial (0C to +70C) | Commercial | Industrial (-40C to +85C) | Commercial | Commercial | Industrial (-40C to +85C) |
| JTAG Support | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Highest speed grade in the 208-pin RQFP MAX 9000 family (vs EPM9320ARC208-15)
- Commercial temperature range version with industrial option available (vs EPM9320ARI208-10)
- Mid-density alternative in PLCC-84 package (vs EPM9320ALC84-10)
Design Notes
Estimated: At 100% utilization (320 macrocells at 144.9 MHz toggle, 5.0 V VCC), the EPM9320ARC208-10 dissipates approximately 1.5-2.5 W. The RQFP-208 package has an integrated heat sink that requires a minimum of 25 cm^2 of PCB copper area beneath the package and 100-200 LFM airflow for reliable operation at maximum frequency. Perform a complete thermal analysis as recommended in Altera Application Note 74 (Evaluating Power for Altera Devices) before committing to high-density designs. Without thermal relief, junction temperature can exceed 125C and trigger intermittent logic faults.
Decoupling is critical for 5V CPLD designs at 144.9 MHz. Place one 0.1 uF ceramic capacitor within 5 mm of each VCC pin (typically 11 VCC pins on the RQFP-208) and a bulk 47-100 uF tantalum or aluminum electrolytic at the board's 5V input. The MAX 9000 datasheet specifies that improper decoupling can cause VCC droop during simultaneous I/O switching, leading to brownout-induced configuration loss. Use a continuous ground plane beneath the device to minimize ground bounce on high-fanout nets.
Common pitfalls when using the EPM9320ARC208-10 include: (1) exceeding 5.0V on any I/O pin (absolute maximum is 7.0V per datasheet, sustained operation at 5.5V stresses EEPROM cells); (2) mixing 3.3V and 5V signals without level-shifters - the MAX 9000 inputs are 5V TTL-compatible but output VOH of 4.4V minimum may not meet 3.3V logic thresholds reliably; (3) forgetting JTAG chain termination if multiple devices share TCK/TMS - install the recommended pull-up on TMS and pull-down on TCK per IEEE 1149.1.
Route JTAG signals (TCK, TMS, TDI, TDO) as a daisy chain with no stubs, keeping total chain length under 15 cm. Per the MAX 9000 datasheet, TCK rise/fall times must remain below 5 ns - use series-damping resistors (22-33 ohm) near the TCK driver if long traces are unavoidable. Place a 10 kohm pull-up on TCK and TMS to keep the JTAG TAP controller in a known state during power-up, preventing accidental JTAG transitions that could reconfigure the device.
Compliance Information
RoHS and lead-free status not confirmed in verified web data; original MAX 9000 family datasheets predate widespread RoHS documentation. Contact Altera (Intel PSG) for material compliance certificates.
