EPM9320ARI208-10N vs EPM9320RC208-10 Comparison
Detailed side-by-side comparison of EPM9320ARI208-10N by Altera and EPM9320RC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteSpecification Comparison
| Parameter | EPM9320ARI208-10N | EPM9320RC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | [DATA_NEEDED: LAB count] |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Supply Voltage | 4.5 V to 5.5 V | 5 V |
| Operating Temperature | -40 C to +85 C (industrial) | Commercial (0C to +70C) - 'C' suffix |
| Package | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (RC) |
| Mounting Type | Surface Mount | — |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS Status | unknown | ROHS3 Compliant (per fpgalink listing) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Speed Grade | — | -10 |
| Programming Interface | — | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Moisture Sensitivity Level (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |