EPM9320RC208-10 - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
MPN: EPM9320RC208-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $39.5 | $395.00 |
| 100 | $34.2 | $3,420.00 |
| 500 | $29.8 | $14,900.00 |
| 1,000 | $26.4 | $26,400.00 |
Drop-in alternatives for EPM9320RC208-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9320RC208-15
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View Datasheet →EPM9320RC208-20
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View Datasheet →EPM9320ARI208-10
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View Datasheet →EPM9320ARI208-10N
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View Datasheet →EPM9320ARC208-10
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View Datasheet →EPM9320ARC208-10N
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View Datasheet →EPM9320RC208-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 |
| Macrocells | 320 |
| Package | 208-pin RQFP (RC) |
| Operating Temperature | Commercial (0C to +70C) - 'C' suffix |
| Supply Voltage | 5 V |
| Speed Grade | -10 |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Lead Time | 1-7 days (per fpgalink listing) |
EPM9320RC208-10 208-pin rqfp (rc) Pin Configuration Guide
Complete pinout information for EPM9320RC208-10 (208-pin rqfp (rc) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9320RC208-10.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320RC208-10 is suitable for 6 applications: Legacy Microprocessor Bus Decoding, Industrial Control Glue Logic, Telecom Infrastructure Backplane Logic, Avionics and Military Legacy Systems, Test and Measurement Equipment, Power Sequencing and Reset Control.
Legacy Microprocessor Bus Decoding
The EPM9320RC208-10 fits legacy 8/16/32-bit microprocessor address decoding thanks to its 320 macrocells and 208-pin RQFP I/O capacity, which provides enough programmable logic to implement full address-decode trees, chip-select generators, and wait-state controllers on Intel 80x86, Motorola 68k, or MIPS buses. With deterministic pin-to-pin tPD typical of MAX 9000 CPLDs, the device introduces well-defined propagation delay into decode paths - critical for legacy CPU subsystems without onboard chipset logic. The non-volatile EPROM-based configuration means the board boots with the decoder logic active instantly, eliminating external boot memory. Compared to discrete 74LS/74F glue logic, a single EPM9320 replaces dozens of decoders and latches, reducing PCB area and improving reliability in industrial single-board computers and telecom control cards. For new designs, MAX II/MAX V equivalents are recommended, but for sustaining legacy 5 V systems the EPM9320RC208-10 remains a practical choice.
Recommended
Industrial Control Glue Logic
The EPM9320RC208-10's 5 V single-supply operation and 320 macrocells make it well-suited to industrial PLC, motor-drive, and process-control board glue logic where 5 V rails remain standard. CPLD non-volatility guarantees the PLC or drive controller powers up in a deterministic state without external configuration memory - essential for safety-critical industrial equipment that must not enter undefined states on brown-out or cold-start. The 208-pin RQFP package provides more than 150 user I/O, enough to interface parallel ADC/DAC buses, encoder inputs, and discrete I/O modules. Industrial temperature variants (EPM9320ARI208-10) share the same die for harsh environments. Compared to multiple discrete PAL/GAL devices, a single EPM9320 simplifies BOM, improves test coverage via JTAG boundary-scan, and allows last-minute logic changes via software updates rather than board respins.
Recommended
Telecom Infrastructure Backplane Logic
The EPM9320RC208-10 serves telecom backplane applications requiring high-I/O-count glue logic, including T1/E1 framer interfacing, HDLC controller bridging, and bus-isolation logic on legacy ATM and SONET line cards. The 208-pin RQFP I/O capacity supports the wide parallel data buses used in 1990s-2000s telecom infrastructure, while the deterministic CPLD timing model simplifies worst-case timing closure across multi-board backplane designs. The non-volatile configuration eliminates the boot-time flash-loading sequence required by SRAM-based FPGAs of similar density, reducing in-service interrupt risk for telecom line cards that must come online instantly. The 5 V supply is compatible with telecom Power-Over-Ethernet and -48 V-to-5 V isolated DC-DC converter rails. For maintaining legacy central-office equipment, the EPM9320RC208-10 is often the only practical substitute for original MAX 9000 designs.
Recommended
Avionics and Military Legacy Systems
The EPM9320RC208-10 in the 208-RQFP package is used in legacy military and avionics subsystems where reliability and long-term availability outweigh density requirements. The MAX 9000 family has extensive flight heritage on platforms dating from the 1990s, and its non-volatile EPROM/EEPROM configuration is immune to radiation-induced configuration upset that affects SRAM FPGAs - a key advantage for avionics and aerospace applications. Industrial temperature variants (EPM9320ARI208-10) extend operating range for avionics bay environments. The deterministic timing supports MIL-STD-1553, ARINC 429, and other legacy avionics bus decoder implementations. For modern redesigns, MAX 10 or radiation-hardened FPGAs are preferred, but for sustaining fielded avionics, the EPM9320 remains the proven incumbent.
Recommended
Test and Measurement Equipment
The EPM9320RC208-10's 320 macrocells and 208-pin RQFP I/O make it appropriate for digital pattern generators, logic analyzers, and protocol testers requiring custom timing and sequencing logic. The deterministic CPLD propagation delay is advantageous in test equipment where synthesized logic must generate precise timing edges to stimulate DUTs. The 5 V I/O compatibility matches legacy TTL/CMOS instrumentation buses (GPIB, VXI), and the JTAG interface supports in-system reconfiguration for different test patterns. Compared to microcontrollers, the CPLD provides deterministic cycle times without interrupt latency - critical for protocol testers. The MAX 9000 family's BitBlaster/ByteBlaster JTAG chain also allows fixture-level programming during test fixture build, accelerating NPI test development.
Recommended
Power Sequencing and Reset Control
The EPM9320RC208-10's 320 macrocells are well-suited to multi-rail power-sequencing controllers used in legacy 5 V/3.3 V/2.5 V mixed-voltage systems. The CPLD can implement reset-generation, watchdog timers, voltage-monitor coordination, and programmable power-up/power-down sequencing across multiple DC-DC converters - replacing discrete supervisory ICs and timer chains. The deterministic pin-to-pin timing ensures repeatable sequencing intervals, while the non-volatile configuration guarantees the correct sequence after brown-out or cold-start. The 208-RQFP I/O count supports sequencing controllers for up to 8-12 independent power rails. JTAG in-system programmability allows sequencing logic updates during board bring-up without hardware changes. For modern PMBus/sequencer IC replacements, the MAX 9000 remains a viable sustaining-solution in field-deployed telecom and industrial equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320RC208-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320RC208-15 | EPM9320RC208-20 | EPM9320ARI208-10 | EPM9320ARC208-10 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin RQFP (RC) | 208-pin RQFP (RC) - same | 208-pin RQFP (RC) - same | 208-pin RQFP (RI) - same footprint | 208-pin RQFP (RC) - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 |
| Speed Grade | -10 | -15 | -20 | -10 | -10 |
| Operating Temperature | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Fastest speed grade in the MAX 9320 RC family (vs EPM9320RC208-15)
- Commercial temperature range for cost-optimized legacy designs (vs EPM9320ARI208-10)
- Non-volatile EPROM configuration for instant-on deterministic boot (vs MAX 10 (SRAM-based) CPLD)
Design Notes
The EPM9320RC208-10 is in NRND (Not Recommended for New Designs) status as of 2026-09-13. Do NOT use this part in new designs. For new CPLD designs, Intel recommends the MAX II (EPM240/G), MAX V (5M240ZE100), or MAX 10 (10M02) families, which require PCB redesign but provide modern features, lower power, and active lifecycle support. The EPM9320RC208-10 should be reserved exclusively for legacy board repair and maintenance.
The 208-pin RQFP package requires careful PCB layout: keep all 208 traces short and matched where bus-impedance matters, use a 4-layer PCB with continuous ground plane under the device for thermal dissipation and EMI suppression, and provide 0.1 uF decoupling capacitors adjacent to every VCC/VCCIO pin pair. JTAG TCK, TMS, TDI, TDO traces should be length-matched and routed away from switching signals to avoid programming-time errors.
The MAX 9000 family uses a 5 V VCCINT and typically 5 V or 3.3 V VCCIO (per-pin I/O bank voltage). When migrating from -10 to -15 or -20 speed grade variants for supply continuity, verify that your timing closure budget tolerates the slower tPD. Estimated: at 25C ambient with typical 5V/3.3V I/O switching activity, the EPM9320 dissipates approximately 0.5-1.5 W - confirm with the MAX 9000 family datasheet ICC vs frequency graph for your design's actual toggle rate.
Compliance Information
RoHS3 compliant per fpgalink listing dated 2026-09-13. MSL-3 moisture sensitivity level. REACH, halogen-free, and conflict-minerals compliance not stated in verified web data - flagged as 'unknown'. AEC-Q100 not applicable - this is a programmable logic IC, not an automotive-grade IC.
