EPM9320RC208-15N vs EPM9320RC208-10 Comparison
Detailed side-by-side comparison of EPM9320RC208-15N by Intel and EPM9320RC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-15N | EPM9320RC208-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Flip-Flops | 484 | — |
| Configurable I/O Lines | 128 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Clock Frequency | 117.6 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Technology | CMOS EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (RC) |
| Terminal Pitch | 0.5 mm | — |
| Operating Temperature Range | 0C to +70C (commercial) | — |
| Mounting Type | Surface Mount | — |
| Packaging | Tray | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink listing) |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Operating Temperature | — | Commercial (0C to +70C) - 'C' suffix |
| Speed Grade | — | -10 |
| Programming Interface | — | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Moisture Sensitivity Level (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |