EPM9320RI208-10N vs EPM9320RC208-20N Comparison
Detailed side-by-side comparison of EPM9320RI208-10N by Altera and EPM9320RC208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RI208-10N | EPM9320RC208-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 9000 | — |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| Supply Voltage | 5 V | 5.0 V |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | 168 |
| Package | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (PowerQuad II) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG/ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature Range | -40C to +85C (industrial) | — |
| RoHS Status | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Lead Finish | Lead-free (matte tin) | [DATA_NEEDED: lead finish] |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Device Family | — | MAX 9000 |
| Logic Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Array Blocks | — | 20 |
| Maximum Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |