EPM9480RC208-15N vs EPM9560ARC208-10N Comparison
Detailed side-by-side comparison of EPM9480RC208-15N by Altera and EPM9560ARC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9480RC208-15N | EPM9560ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 10,000 | 12,000 |
| Macro Cells | 480 | — |
| Maximum Frequency | 117.6 MHz | — |
| Propagation Delay | 15 ns (speed grade -15) | — |
| Supply Voltage | 5.0 V | 5 V |
| Package | 208-pin RQFP | 208-pin RQFP (PowerQuad II) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (ISP via JTAG) | Yes (JTAG ISP) |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| RoHS Status | ROHS3 Compliant | Compliant (N suffix) |
| Moisture Sensitivity Level | MSL 3 (168 Hours) | — |
| Manufacturer Standard Lead Time | 1-7 Days | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| Macrocells | — | 560 |
| User I/O Pins | — | 153 |
| Pin-to-Pin Delay | — | 10 ns |
| Internal Counter Frequency | — | 144.9 MHz |
| Technology | — | CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 20 |
| Speed Grade | — | -10 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL Level | — | [DATA_NEEDED: MSL level] |