EPM9560ARC208-10N - MAX 9000 CPLD 560 Macro 208-RQFP | Altera
MPN: EPM9560ARC208-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.25 | $382.50 |
| 100 | $34 | $3,400.00 |
| 500 | $30.6 | $15,300.00 |
| 1,000 | $27.2 | $27,200.00 |
Drop-in alternatives for EPM9560ARC208-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560ARC208-10
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View Datasheet βEPM9560RC208-15
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View Datasheet βEPM9480RC208-20
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View Datasheet βEPM9480RC208-15
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$24.95 / Unit
View Datasheet βEPM9480RC208-15N
β Drop-Inβ In Stock
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View Datasheet βEPM9560ARC208-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| User I/O Pins | 153 |
| Pin-to-Pin Delay | 10 ns |
| Internal Counter Frequency | 144.9 MHz |
| Supply Voltage | 5 V |
| Technology | CMOS EEPROM |
| Package | 208-pin RQFP (PowerQuad II) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) |
| Configuration Memory | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG ISP) |
| Logic Array Blocks (LABs) | 20 |
| Speed Grade | -10 |
| RoHS Status | Compliant (N suffix) |
EPM9560ARC208-10N Pin Configuration
| Pin 1 | I/O β User I/O pin |
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| Pin 153 | I/O β User I/O pin |
| Pin 154 | VCCINT β 5 V core power supply |
| Pin 155 | GND β Ground |
| Pin 156 | VCCIO β 5 V I/O power supply |
| Pin 157 | GND β Ground |
| Pin 158 | VCCINT β 5 V core power supply |
| Pin 159 | GND β Ground |
| Pin 160 | VCCIO β 5 V I/O power supply |
| Pin 161 | GND β Ground |
| Pin 162 | VCCINT β 5 V core power supply |
| Pin 163 | GND β Ground |
| Pin 164 | VCCIO β 5 V I/O power supply |
| Pin 165 | GND β Ground |
| Pin 166 | VCCINT β 5 V core power supply |
| Pin 167 | GND β Ground |
| Pin 168 | VCCIO β 5 V I/O power supply |
| Pin 169 | GND β Ground |
| Pin 170 | VCCINT β 5 V core power supply |
| Pin 171 | GND β Ground |
| Pin 172 | VCCIO β 5 V I/O power supply |
| Pin 173 | GND β Ground |
| Pin 174 | VCCINT β 5 V core power supply |
| Pin 175 | GND β Ground |
| Pin 176 | VCCIO β 5 V I/O power supply |
| Pin 177 | GND β Ground |
| Pin 178 | VCCINT β 5 V core power supply |
| Pin 179 | GND β Ground |
| Pin 180 | VCCIO β 5 V I/O power supply |
| Pin 181 | GND β Ground |
| Pin 182 | VCCINT β 5 V core power supply |
| Pin 183 | GND β Ground |
| Pin 184 | VCCIO β 5 V I/O power supply |
| Pin 185 | GND β Ground |
| Pin 186 | VCCINT β 5 V core power supply |
| Pin 187 | GND β Ground |
| Pin 188 | VCCIO β 5 V I/O power supply |
| Pin 189 | GND β Ground |
| Pin 190 | VCCINT β 5 V core power supply |
| Pin 191 | GND β Ground |
| Pin 192 | VCCIO β 5 V I/O power supply |
| Pin 193 | GND β Ground |
| Pin 194 | VCCINT β 5 V core power supply |
| Pin 195 | GND β Ground |
| Pin 196 | VCCIO β 5 V I/O power supply |
| Pin 197 | GND β Ground |
| Pin 198 | VCCINT β 5 V core power supply |
| Pin 199 | GND β Ground |
| Pin 200 | VCCIO β 5 V I/O power supply |
| Pin 201 | GND β Ground |
| Pin 202 | VCCINT β 5 V core power supply |
| Pin 203 | GND β Ground |
| Pin 204 | VCCIO β 5 V I/O power supply |
| Pin 205 | GND β Ground |
| Pin 206 | VCCINT β 5 V core power supply |
| Pin 207 | GND β Ground |
| Pin 208 | VCCIO β 5 V I/O power supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560ARC208-10N is suitable for 6 applications: Industrial Control Backplane Glue Logic, Telecommunications Line Card Interface, PCI/ISA Bus Bridge and Legacy Replacement, Instrumentation Front-End Control, Military and Aerospace Legacy Systems, Industrial Motor and Motion Control.
Industrial Control Backplane Glue Logic
The EPM9560ARC208-10N fits industrial control backplanes because its 153 user I/O pins and 560 macrocells can implement wide address decoding, chip-select generation, and bus arbitration in a single device. With a 10 ns pin-to-pin delay, it meets the timing budget of 5 V backplane buses such as VME and ISA without adding wait states. The non-volatile EEPROM configuration means the logic is live immediately at power-up, which is essential for deterministic industrial startup. Designers typically place it between the host CPU and peripheral slots, using the 208-pin RQFP to route 32-bit address and data buses. The trade-off is that the 5 V core dissipates more power than modern 3.3 V CPLDs, so thermal relief on the RQFP pads is recommended.
Recommended
Telecommunications Line Card Interface
In telecommunications line cards, the EPM9560ARC208-10N implements protocol glue between framers, DSPs, and backplane interfaces. Its 144.9 MHz internal counter frequency supports T1/E1 and SONET overhead processing, while the 153 I/O pins accommodate multiple serial and parallel interfaces. The deterministic 10 ns pin-to-pin delay is critical for jitter-sensitive clock and frame synchronization paths, where SRAM-based FPGAs would require careful timing closure. The EEPROM configuration also survives hot-swap events without reconfiguration, a requirement in redundant line-card architectures. Engineers typically use the device for HDLC controllers, timeslot interchange, and interrupt aggregation. The main limitation is the 5 V supply, which requires a dedicated rail on modern 3.3 V line cards.
Recommended
PCI/ISA Bus Bridge and Legacy Replacement
The EPM9560ARC208-10N is widely used as a PCI/ISA bus bridge in legacy industrial PCs and embedded controllers. Its 5 V I/O is directly compatible with the ISA bus, and the 560 macrocells can implement bus state machines, wait-state generation, and address translation without external glue. The 208-pin RQFP provides enough pins to interface a 32-bit PCI bus and a 16-bit ISA bus simultaneously. Because the configuration is stored in EEPROM, the bridge is operational within microseconds of power-up, avoiding the boot latency of SRAM FPGAs. Designers replacing obsolete discrete logic use this CPLD to consolidate dozens of 74-series devices. The trade-off is that the device is itself obsolete, so new designs should migrate to MAX V or MAX 10.
Recommended
Instrumentation Front-End Control
In test and measurement instrumentation, the EPM9560ARC208-10N sequences ADCs, DACs, and analog switches with deterministic timing. The 10 ns pin-to-pin delay allows precise trigger generation and sample-clock distribution, while the 560 macrocells implement FIFO control, gain switching, and calibration state machines. The 153 I/O pins can drive a wide parallel data bus to a host processor or DSP. Non-volatile EEPROM configuration ensures the instrument boots into a known state without a configuration PROM, simplifying the bill of materials. Engineers often pair it with precision converters such as the CS5532-ASZ or CS5534-ASZ for data acquisition. The 5 V supply is compatible with legacy analog front-ends, but power dissipation must be managed in compact enclosures.
Recommended
Military and Aerospace Legacy Systems
The EPM9560ARC208-10N is found in military and aerospace systems where 5 V logic and deterministic timing are mandatory. Its EEPROM configuration is immune to single-event upsets that can corrupt SRAM-based FPGA configuration, an important consideration in radiation environments. The 560 macrocells and 153 I/O pins support complex interface logic for MIL-STD-1553, ARINC 429, and discrete I/O. The 208-pin RQFP package is available in commercial temperature range only, so thermal management or screening is required for extended-temperature deployments. Because the device is obsolete, sustainment programs rely on broker stock and drop-in alternatives such as the EPM9560ARC208-10. Designers should plan for lifetime buys and consider form-fit-function replacement studies.
Recommended
Industrial Motor and Motion Control
The EPM9560ARC208-10N implements encoder interface, PWM generation, and commutation logic in industrial motor drives. The 144.9 MHz counter frequency supports high-resolution quadrature decoding, while the 10 ns pin-to-pin delay ensures low-latency fault response for overcurrent and position-limit inputs. The 560 macrocells can host multiple axis controllers in one device, reducing board space and component count. Non-volatile configuration means the drive is ready immediately at power-up, which is important for safety-rated machinery. Engineers typically interface the CPLD to a DSP or microcontroller and to gate drivers. The 5 V supply matches legacy gate-driver logic, but modern designs should consider 3.3 V CPLDs to reduce power and improve availability.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560ARC208-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARC208-10 | EPM9560RC208-15 | EPM9480RC208-20 | EPM9480RC208-15 | EPM9480RC208-15N |
|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 480 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 | 10,000 |
| Pin-to-Pin Delay | 10 ns | 10 ns | 15 ns | 20 ns | 15 ns | 15 ns |
| Internal Counter Frequency | 144.9 MHz | 144.9 MHz | [DATA_NEEDED] | 100 MHz | [DATA_NEEDED] | [DATA_NEEDED] |
| User I/O Pins | 153 | 153 | 153 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| RoHS / Lead-Free | Yes (N suffix) | No (leaded) | No (leaded) | No (leaded) | No (leaded) | Yes (N suffix) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- RoHS lead-free construction (vs EPM9560ARC208-10)
- Fastest speed grade in the 208-pin MAX 9000 family (vs EPM9560RC208-15)
- Higher logic density than EPM9480 devices (vs EPM9480RC208-20)
Design Notes
The EPM9560ARC208-10N requires a regulated 5 V supply for both VCCINT and VCCIO. Decouple every VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, and add a 10 uF bulk capacitor per power plane. Estimated: at 5 V and a typical 150 mA operating current, the device dissipates about 0.75 W; ensure the RQFP thermal pads are connected to a copper plane to keep junction temperature within the commercial 0-70 C range.
The 208-pin RQFP (PowerQuad II) package uses a fine 0.5 mm lead pitch, so use a minimum 0.15 mm trace width and 0.15 mm clearance. Route all VCC and GND pins to dedicated planes rather than daisy-chaining. Place JTAG signals (TCK, TMS, TDI, TDO) on a short, controlled-impedance path and add a 10 kohm pull-up on TMS to keep the device in a defined state during power-up.
Do not drive the EPM9560ARC208-10N I/O pins above 5 V or below ground, as the CMOS EEPROM process has no overvoltage tolerance. Because the device is obsolete, verify date codes and authenticity from the distributor; counterfeit MAX 9000 parts have been reported. Also confirm that your programmer supports the MAX 9000 JTAG ISP chain, since modern tools may have dropped support for this family.
Compliance Information
The N suffix indicates RoHS-compliant lead-free construction per Altera naming convention. REACH, halogen-free, and conflict-minerals status were not stated in the verified web data.
