EPM9560ARC208-10N vs EPM9480RC208-15N Comparison
Detailed side-by-side comparison of EPM9560ARC208-10N by Altera and EPM9480RC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560ARC208-10N | EPM9480RC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 10,000 |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Internal Counter Frequency | 144.9 MHz | — |
| Supply Voltage | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Package | 208-pin RQFP (PowerQuad II) | 208-pin RQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG ISP) | Yes (ISP via JTAG) |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | — |
| RoHS Status | Compliant (N suffix) | ROHS3 Compliant |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 480 |
| Maximum Frequency | — | 117.6 MHz |
| Propagation Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Moisture Sensitivity Level | — | MSL 3 (168 Hours) |
| Manufacturer Standard Lead Time | — | 1-7 Days |
| Architecture | — | Multiple Array MatriX (MAX) third-generation |