EPM9560ARC304-10F vs EPM9560RC304-15F Comparison

Detailed side-by-side comparison of EPM9560ARC304-10F by Altera and EPM9560RC304-15F by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARC304-10F EPM9560RC304-15F
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $18.75
Device Family MAX 9000A MAX 9000
Programmable Type In System Programmable (ISP) β€”
Number of Macrocells 560 β€”
Number of Logic Elements/Blocks 35 LABs β€”
Number of Gates 12000 β€”
Number of I/O 216 β€”
Maximum Delay Time (tPD) 10 ns β€”
Supply Voltage (Internal) 4.75 V to 5.25 V β€”
Operating Temperature 0 C to +70 C (commercial) -40C to +85C (industrial)
Package 304-pin RQFP (PowerQuad II) RQFP-304 (304-pin Plastic QFP)
Package Code FQFP β€”
Terminal Form Gull Wing β€”
Package Shape Square β€”
Mounting Type Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) β€”
JTAG Support IEEE 1149.1 (ISP) β€”
RoHS Status RoHS [DATA_NEEDED: rohs status - not stated in source]
Speed Grade -10 (10 ns) β€”
Series β€” EPM9560
Macrocells β€” 560
Usable Gates β€” 12,000
Propagation Delay (tpd) β€” 16.6 ns (max)
Maximum Internal Frequency β€” 117.6 MHz
Core Supply Voltage β€” 5.0 V
User I/O Pins β€” 212
Dedicated Inputs β€” 4
Logic Array Blocks (LABs) β€” 16 (40 macrocells each)
Programming Technology β€” 5.0 V in-system EEPROM via JTAG (IEEE 1149.1)
Architecture β€” Multiple Array MatriX (MAX) with PIA interconnect
Boundary Scan Test (BST) β€” Yes, JTAG-compliant
Process Technology β€” High-performance CMOS, EEPROM-based
MSL Level β€” 3 (168 hours)

Datasheets & Resources

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