EPM9560ARC304-10F vs EPM9560RC304-15F Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARC304-10F sa pamamagitan ng Altera at EPM9560RC304-15F sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560ARC304-10F | EPM9560RC304-15F |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | MAX 9000A | MAX 9000 |
| Programmable Type | In System Programmable (ISP) | — |
| Number of Macrocells | 560 | — |
| Number of Logic Elements/Blocks | 35 LABs | — |
| Number of Gates | 12000 | — |
| Number of I/O | 216 | — |
| Maximum Delay Time (tPD) | 10 ns | — |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Packhaging | 304-pin RQFP (PowerQuad II) | RQFP-304 (304-pin Plastic QFP) |
| Package Code | FQFP | — |
| Terminal Form | Gull Wing | — |
| Package Shape | Square | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Support | IEEE 1149.1 (ISP) | — |
| Tindminan RoHS | RoHS | [DATA_NEEDED: rohs status - not stated in source] |
| Speed Grade | -10 (10 ns) | — |
| Series | — | EPM9560 |
| Macrocells | — | 560 |
| Usable Gates | — | 12,000 |
| Propagation Delay (tpd) | — | 16.6 ns (max) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Core Supply Voltage | — | 5.0 V |
| User I/O Pins | — | 212 |
| Dedicated Inputs | — | 4 |
| Logic Array Blocks (LABs) | — | 16 (40 macrocells each) |
| Programming Technology | — | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| Architecture | — | Multiple Array MatriX (MAX) with PIA interconnect |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Process Technology | — | High-performance CMOS, EEPROM-based |
| Level ng MSL | — | 3 (168 hours) |