EPM9560ARI208-10N vs EPM9560ARI240-10 Comparison
Detailed side-by-side comparison of EPM9560ARI208-10N by Altera and EPM9560ARI240-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N ObsoleteSpecification Comparison
| Parameter | EPM9560ARI208-10N | EPM9560ARI240-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Maximum User I/O Pins | 212 | — |
| Flip-Flops | 484 | — |
| Propagation Delay (tPD1) | 10 ns | — |
| Clock-to-Output (tCO) | 4.5 ns | — |
| Setup Time (tSU) | 3.0 ns | — |
| Maximum Counter Frequency (fCNT) | 144.9 MHz | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Logic Family | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE 1149.1) - In-System Programmable | — |
| Package | 208-pin RQFP (Plastic) | 240-pin RQFP (PowerQuad Flat Pack) |
| Operating Temperature | 0 C to 70 C (Commercial) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 560 |
| User I/O Pins | — | 191 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Internal Frequency | — | 144.9 MHz |
| Technology | — | CMOS, EEPROM-based configuration |
| Operating Temperature Range | — | -40 C to +85 C (industrial) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| Logic Architecture | — | Multiple Array MatriX (MAX) with global interconnect array |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |
| Number of Terminals | — | 240 |
| Terminal Form | — | Gull Wing |