EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
MPN: EPM9560ARI208-10N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 250 | $25.4 | $6,350.00 |
| 500 | $22.1 | $11,050.00 |
Drop-in alternatives for EPM9560ARI208-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560ARC208-10N
✅ Drop-In✓ In Stock
$27.2 / Unit
View Datasheet →EPM9560ARC208-10
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPM9560ARI208-10
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPM9320ARI208-10N
✅ Drop-In✓ In Stock
$16.2 / Unit
View Datasheet →EPM9480RC208-15
✅ Drop-In✓ In Stock
$24.95 / Unit
View Datasheet →EPM9560ARI208-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| Maximum User I/O Pins | 212 |
| Flip-Flops | 484 |
| Propagation Delay (tPD1) | 10 ns |
| Clock-to-Output (tCO) | 4.5 ns |
| Setup Time (tSU) | 3.0 ns |
| Maximum Counter Frequency (fCNT) | 144.9 MHz |
| Supply Voltage | 5.0 V |
| Logic Family | CMOS EEPROM |
| Programming Interface | JTAG (IEEE 1149.1) - In-System Programmable |
| Package | 208-pin RQFP (Plastic) |
| Operating Temperature | 0 C to 70 C (Commercial) |
| Mounting Type | Surface Mount |
EPM9560ARI208-10N 208-pin rqfp (plastic) Pin Configuration Guide
Complete pinout information for EPM9560ARI208-10N (208-pin rqfp (plastic) package) with 212 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560ARI208-10N.
Refer to the datasheet for full pin configuration.
Estimated pin count: 212 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560ARI208-10N is suitable for 6 applications: Legacy Peripheral Bus Interfacing (ISA / VME), Memory Address Decoding and Chip-Select Generation, State-Machine Protocol Converters, Industrial Glue-Logic Integration, Test and Measurement Equipment Backplane Logic, Legacy Telecom and Networking Interface Cards.
Legacy Peripheral Bus Interfacing (ISA / VME)
The EPM9560ARI208-10N is well suited for ISA and VME peripheral bus glue logic, where its 153 user I/O pins and 560 macrocells can decode addresses, generate chip selects, and arbitrate interrupts without external TTL. Its deterministic 10 ns pin-to-pin propagation delay (tPD) and 4.5 ns clock-to-output (tCO) meet the ISA bus 8 MHz timing budget with margin, while the 5.0 V tolerance matches legacy bus signaling. Unlike SRAM-based FPGAs, the EEPROM-based MAX 9000 retains configuration at power-up, eliminating the boot-memory overhead common in industrial backplane designs.
Recommended
Memory Address Decoding and Chip-Select Generation
With 560 macrocells and 35 Logic Array Blocks, the EPM9560ARI208-10N can replace dozens of 22V10, PAL, and GAL devices in memory decoding trees for 16- and 32-bit systems. The programmable interconnect array (PIA) delivers fan-in without speed penalty, and the 4.5 ns tCO timing supports zero-wait-state decoding for 33 MHz microprocessors. The EEPROM process gives 100 program/erase cycles and 20-year retention, making it appropriate for production memory subsystems that may require occasional field updates via JTAG.
Recommended
State-Machine Protocol Converters
The EPM9560ARI208-10N's 484 flip-flops and high counter frequency (144.9 MHz fCNT) make it ideal for serial protocol conversion between UART, SPI, I2C, and proprietary industrial buses. Its deterministic timing allows precise bit-banging of low-speed protocols with predictable latency, while the 12K usable gates fit entire multi-state converters plus auxiliary logic. The non-volatile EEPROM configuration makes the device suitable for industrial equipment that must boot to a known state without external memory.
Recommended
Industrial Glue-Logic Integration
The EPM9560ARI208-10N consolidates multiple discrete PLDs (PAL, GAL, 22V10) into a single 208-pin RQFP, reducing board area, BOM count, and inventory SKUs in industrial automation equipment. The 153 available user I/O pins accept wide parallel buses, multiple encoder inputs, and discrete control signals. The 5.0 V tolerance interfaces directly with TTL and CMOS logic families common in legacy industrial controllers, and the JTAG ISP enables in-field firmware updates for retrofits and upgrades.
Recommended
Test and Measurement Equipment Backplane Logic
Test equipment benefits from the EPM9560ARI208-10N's deterministic timing and high I/O count for instrument backplane switching, trigger routing, and timing generation. The 144.9 MHz fCNT supports precise counter and timer implementations, while the 560 macrocells provide room for trigger sequencers and arbiter logic. The non-volatile configuration ensures the instrument boots to a known test configuration, and the JTAG boundary-scan (IEEE 1149.1) aids board-level test coverage in production.
Recommended
Legacy Telecom and Networking Interface Cards
The EPM9560ARI208-10N is well suited to legacy telecom line cards and network interface adapters where 5.0 V I/O, deterministic timing, and non-volatile boot are required. Its 153 user I/O pins accept TDM bus data, control lines, and status indicators, while the 10 ns tPD enables glue-logic pipelines operating at telecom system clock rates. The EEPROM configuration makes the part ideal for ruggedized outdoor equipment where external boot memory is undesirable.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560ARI208-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARC208-10N | EPM9560ARC208-10 | EPM9560ARI208-10 | EPM9320ARI208-10N | EPM9480RC208-15 |
|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | 320 (-43%) | 480 (-14%) |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 6,000 (-50%) | 10,000 (-17%) |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 15 ns (+50%) |
| Counter Frequency (fCNT) | 144.9 MHz | 144.9 MHz | 144.9 MHz | 144.9 MHz | 144.9 MHz | 118 MHz (-19%) |
| Lead-Free / RoHS | Yes (N suffix) | Yes (N suffix) | No (SnPb) | No (SnPb) | Yes (N suffix) | No (SnPb) |
| User I/O (208-RQFP variant) | 153 | 153 | 153 | 153 | 112 | 146 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest macrocell density in MAX 9000 family (vs EPM9480RC208-15)
- Fastest 10 ns speed grade available in 208-RQFP (vs EPM9480RC208-15)
- Lead-free RoHS-compliant finish (vs EPM9560ARI208-10)
Design Notes
Estimated: The EPM9560ARI208-10N operates from a single 5.0 V supply with multiple VCC and GND pins distributed across the 208-pin RQFP package. Place one 0.1 uF decoupling capacitor adjacent to each VCC/GND pair, and add a single 10 uF bulk capacitor near the package supply entry. The CMOS EEPROM core draws standby current well under 100 mA in static operation; peak current during in-system programming (ISP) via JTAG is higher - check the MAX 9000 datasheet Icc specification for the exact ISP surge budget.
Use a 4-layer PCB with continuous ground plane for the 208-pin RQFP. The RQFP has 0.5 mm pitch leads that require precise land pattern adherence to the IPC-7351 nominal footprint. Assign JTAG pins (TDI, TDO, TMS, TCK) to dedicated board test points or a JTAG header for in-system programming and IEEE 1149.1 boundary-scan. Keep clock inputs (GCLK1, GCLK2, GCLK3) on dedicated input pins per the datasheet, with trace lengths matched if multiple clocks are used.
Critical: The EPM9560ARI208-10N is obsolete and not recommended for new designs. For new production in 2026, design with active parts such as Intel MAX V (5M160ZE64C5N) or MAX 10 (10M08SCE144I7G) CPLDs that share the Quartus toolchain. If the design must remain on the EPM9560 for legacy compatibility, validate long-term supply with multiple aftermarket distributors and qualify a second-source Altera/Intel part (EPM9560ARC208-10N or EPM9480RC208-15) as a backup.
The EPM9560ARI208-10N provides 5.0 V CMOS-compatible I/O with deterministic 10 ns propagation delay. For high-speed busses operating above 50 MHz, use series damping resistors (22-33 ohm) near the CPLD output to control ringing on the RQFP leads. The 208-pin RQFP lead inductance (~2-3 nH per lead) is sufficient to cause overshoot on fast edges; a small series resistor or ferrite bead mitigates this without affecting timing margin.
Compliance Information
Lead-free terminal finish indicated by N suffix. AEC-Q100 not applicable - this is a commercial-grade logic device. REACH and halogen-free status not documented in available verified data.
