EPM9560GC280-15 vs EPM9560GI280-20 Comparison
Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560GI280-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560GC280-15 | EPM9560GI280-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $115.00 | $162.50 |
| Family | MAX 9000 | β |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | β |
| Macro Cells | 560 | β |
| Typical Gates | 12,000 | β |
| Maximum Operating Frequency | 117.6 MHz | β |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | β |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Operating Temperature (Commercial) | 0C to +70C | β |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | β |
| Mounting Type | Through-Hole | β |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | β |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | β |
| Architecture | Multiple Array MatriX (MAX) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| RoHS Status | Non-compliant (ceramic CPGA, contains lead) | [DATA_NEEDED: RoHS status for GI PGA package] |
| Lifecycle Status | Obsolete (legacy Altera MAX 9000 family) | β |
| Device Family | β | MAX 9000 |
| Technology Node | β | 5.0 V CMOS EEPROM |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 28 (16 macrocells each) |
| Usable Gates | β | 12,000 |
| Maximum User I/O Pins | β | 216 |
| Flip-Flops | β | 772 |
| Pin-to-Pin Delay (Speed Grade) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| In-System Programmability | β | Yes (IEEE Std. 1149.1 JTAG) |
| Programming Technology | β | EEPROM (non-volatile) |
| Package | β | 280-pin PGA (PIN/PEG, square) |
| Terminal Form | β | PIN/PEG (through-hole PGA) |
| Package Code | β | PGA |
| Temperature Grade | β | Industrial |
| I/O Pin DC Input Range | β | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | β | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | β | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | β | Monotonic rise |
| Development Tool | β | Altera MAX+PLUS II |
| Supported HDLs | β | VHDL, Verilog HDL, AHDL |