EPM9560R1208-20 vs EPM9560GI280-20 Comparison
Detailed side-by-side comparison of EPM9560R1208-20 by Altera and EPM9560GI280-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560R1208-20
EPM9560R1208-20 - MAX 9000 CPLD 6k Gates 1208-pin | Altera
EPM9560R1208-20 ObsoleteIntel
EPM9560GI280-20
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
EPM9560GI280-20 NrndSpecification Comparison
| Parameter | EPM9560R1208-20 | EPM9560GI280-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.40 | $162.50 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks | 52 (typical for 560 macrocells) | β |
| Maximum User I/O | 212 | β |
| Propagation Delay (tPD) | 20 ns | β |
| Maximum Frequency (fMAX) | 125 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| Operating Temperature | 0C to +70C (commercial) | β |
| Package | R-1208 (BGA-style fine-pitch) | 280-pin PGA (PIN/PEG, square) |
| Mounting Type | Surface Mount | β |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | β |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | β |
| Configuration Memory | On-chip EEPROM (non-volatile) | β |
| RoHS Status | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Device Family | β | MAX 9000 |
| Technology Node | β | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | β | 28 (16 macrocells each) |
| Maximum User I/O Pins | β | 216 |
| Flip-Flops | β | 772 |
| Pin-to-Pin Delay (Speed Grade) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| Programming Technology | β | EEPROM (non-volatile) |
| Terminal Form | β | PIN/PEG (through-hole PGA) |
| Package Code | β | PGA |
| Temperature Grade | β | Industrial |
| I/O Pin DC Input Range | β | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | β | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | β | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | β | Monotonic rise |
| Development Tool | β | Altera MAX+PLUS II |
| Supported HDLs | β | VHDL, Verilog HDL, AHDL |