EPM9560R1208-20 vs EPM9560GI280-20 比較
詳細な並列比較: EPM9560R1208-20 メーカー: Altera および EPM9560GI280-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560R1208-20 | EPM9560GI280-20 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $22.40 | $162.50 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks | 52 (typical for 560 macrocells) | — |
| Maximum User I/O | 212 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| 動作温度 | 0C to +70C (commercial) | — |
| パッケージ | R-1208 (BGA-style fine-pitch) | 280-pin PGA (PIN/PEG, square) |
| 実装タイプ | Surface Mount | — |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | — |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| RoHS ステータス | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Device Family | — | MAX 9000 |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 28 (16 macrocells each) |
| Maximum User I/O Pins | — | 216 |
| Flip-Flops | — | 772 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programming Technology | — | EEPROM (non-volatile) |
| Terminal Form | — | PIN/PEG (through-hole PGA) |
| Package Code | — | PGA |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |