EPM9560RC208-15 vs EPM9480RC208-15N Comparison
Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9480RC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-15 | EPM9480RC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 gates | 10,000 |
| Macro Cells | 560 macro cells | 480 |
| Pin-to-Pin Delay | 15 ns | β |
| Counter Speed | 117.6 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | β |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Speed Grade | -15 (15 ns pin-to-pin) | β |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) third-generation |
| Maximum Frequency | β | 117.6 MHz |
| Propagation Delay | β | 15 ns (speed grade -15) |
| Configuration Memory | β | EEPROM (non-volatile) |
| JTAG Interface | β | IEEE Std. 1149.1 |
| Moisture Sensitivity Level | β | MSL 3 (168 Hours) |
| Manufacturer Standard Lead Time | β | 1-7 Days |