EPM9560RC208-15 vs EPM9480RC208-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-15 sa pamamagitan ng Altera at EPM9480RC208-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-15 | EPM9480RC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 gates | 10,000 |
| Macro Cells | 560 macro cells | 480 |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| Volte ng Pagbibigay | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Speed Grade | -15 (15 ns pin-to-pin) | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) third-generation |
| Maximum Frequency | — | 117.6 MHz |
| Propagation Delay | — | 15 ns (speed grade -15) |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Moisture Sensitivity Level | — | MSL 3 (168 Hours) |
| Manufacturer Standard Lead Time | — | 1-7 Days |