EPM9560RC208-15 vs EPM9560RC208-12 Comparison
Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9560RC208-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-15 | EPM9560RC208-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | EEPROM-based CPLD |
| Usable Gates | 12,000 gates | 12000 |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| Supply Voltage | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (S-PQFP-G208) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | 20 |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | -12 (12 ns) |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Clock Frequency | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.50 mm |
| Configuration Memory | — | EEPROM (non-volatile) |