EPM9560RC208-15 vs EPM9560RC208-12 对比
详细并排对比 EPM9560RC208-15 出自 Altera 和 EPM9560RC208-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560RC208-15 | EPM9560RC208-12 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | EEPROM-based CPLD |
| Usable Gates | 12,000 gates | 12000 |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| 电源电压 | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封装 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (S-PQFP-G208) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | 20 |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | -12 (12 ns) |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Propagation Delay (tPD) | — | 12 ns |
| 最大时钟频率 | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.50 mm |
| Configuration Memory | — | EEPROM (non-volatile) |