EPM9560RC208-15 vs EPM9560RC208-15N Comparison
Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9560RC208-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteIntel
EPM9560RC208-15N
EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP
EPM9560RC208-15N β Last Time BuySpecification Comparison
| Parameter | EPM9560RC208-15 | EPM9560RC208-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $19.85 |
| Family | MAX 9000 | β |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 macro cells | β |
| Pin-to-Pin Delay | 15 ns | β |
| Counter Speed | 117.6 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | β |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] |
| Speed Grade | -15 (15 ns pin-to-pin) | -15 (15 ns tPD) |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - third generation |
| Series | β | MAX 9000 |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 16 |
| User I/O | β | 212 (in 208-RQFP, see family datasheet) |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Maximum Internal Frequency | β | 117.6 MHz |
| Supply Voltage (VCCINT) | β | 5.0 V |
| Programmability | β | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | β | CMOS EEPROM (non-volatile) |
| Operating Temperature (commercial) | β | 0C to +70C |