EPM9560RC208-15C vs EPM9560RC208-19 Comparison
Detailed side-by-side comparison of EPM9560RC208-15C by Altera and EPM9560RC208-19 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-15C | EPM9560RC208-19 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based CPLD (EPLD) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 149 | 149 |
| Propagation Delay (tPD) | 15 ns | 19 ns |
| Maximum Counter Frequency | 117.6 MHz | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE 1149.1 JTAG) |
| Package | 208-pin RQFP | RQFP-208 (208-pin PQFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) | — |
| Speed Grade | -15 (15 ns) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX) third generation | — |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Flip-Flops | — | 772 |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V / 5 V |
| Technology | — | CMOS EEPROM |
| JEDEC Package Code | — | S-PQFP-G208 |
| Operating Temperature | — | [DATA_NEEDED: operating temperature grade] |