EPM9560RC208-19 - MAX 9000 CPLD, 560 Macrocells, 19ns | Altera
MPN: EPM9560RC208-19 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.95 | $249.50 |
| 100 | $21.4 | $2,140.00 |
| 500 | $18.75 | $9,375.00 |
| 1,000 | $16.2 | $16,200.00 |
Drop-in alternatives for EPM9560RC208-19 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC208-15
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View Datasheet →EPM9560RC208-17
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View Datasheet →EPM9560RC208-18
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View Datasheet →EPM9560RC208-20
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View Datasheet →EPM9560RC208-20C
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View Datasheet →EPM9560RC208-15N
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$19.85 / Unit
View Datasheet →EPM9560RC208-15C
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View Datasheet →EPM9560RC208-19 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Flip-Flops | 772 |
| User I/O Pins | 149 |
| Propagation Delay (tPD) | 19 ns |
| Supply Voltage (VCCINT) | 5.0 V |
| I/O Voltage Tolerance | 3.3 V / 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Technology | CMOS EEPROM |
| Package | RQFP-208 (208-pin PQFP) |
| JEDEC Package Code | S-PQFP-G208 |
| Mounting Type | Surface Mount |
EPM9560RC208-19 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | VCCIO1 — I/O supply voltage bank 1 (3.3V or 5V) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | I/O — User I/O pin (bank 1) |
| Pin 16 | I/O — User I/O pin (bank 1) |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 1) |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | I/O — User I/O pin (bank 2) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | I/O — User I/O pin (bank 2) |
| Pin 27 | I/O — User I/O pin (bank 2) |
| Pin 28 | I/O — User I/O pin (bank 2) |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | I/O — User I/O pin (bank 2) |
| Pin 31 | I/O — User I/O pin (bank 2) |
| Pin 32 | I/O — User I/O pin (bank 2) |
| Pin 33 | VCCIO2 — I/O supply voltage bank 2 (3.3V or 5V) |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | I/O — User I/O pin (bank 2) |
| Pin 37 | I/O — User I/O pin (bank 2) |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | I/O — User I/O pin (bank 2) |
| Pin 40 | I/O — User I/O pin (bank 2) |
| Pin 41 | I/O — User I/O pin (bank 2) |
| Pin 42 | I/O — User I/O pin (bank 2) |
| Pin 43 | GND — Ground |
| Pin 44 | I/O — User I/O pin (bank 3) |
| Pin 45 | I/O — User I/O pin (bank 3) |
| Pin 46 | I/O — User I/O pin (bank 3) |
| Pin 47 | I/O — User I/O pin (bank 3) |
| Pin 48 | I/O — User I/O pin (bank 3) |
| Pin 49 | I/O — User I/O pin (bank 3) |
| Pin 50 | I/O — User I/O pin (bank 3) |
| Pin 51 | I/O — User I/O pin (bank 3) |
| Pin 52 | I/O — User I/O pin (bank 3) |
| Pin 53 | I/O — User I/O pin (bank 3) |
| Pin 54 | I/O — User I/O pin (bank 3) |
| Pin 55 | VCCIO3 — I/O supply voltage bank 3 (3.3V or 5V) |
| Pin 56 | I/O — User I/O pin (bank 3) |
| Pin 57 | I/O — User I/O pin (bank 3) |
| Pin 58 | I/O — User I/O pin (bank 3) |
| Pin 59 | I/O — User I/O pin (bank 3) |
| Pin 60 | I/O — User I/O pin (bank 3) |
| Pin 61 | I/O — User I/O pin (bank 3) |
| Pin 62 | I/O — User I/O pin (bank 3) |
| Pin 63 | I/O — User I/O pin (bank 3) |
| Pin 64 | I/O — User I/O pin (bank 3) |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — User I/O pin (bank 4) |
| Pin 67 | I/O — User I/O pin (bank 4) |
| Pin 68 | I/O — User I/O pin (bank 4) |
| Pin 69 | I/O — User I/O pin (bank 4) |
| Pin 70 | I/O — User I/O pin (bank 4) |
| Pin 71 | I/O — User I/O pin (bank 4) |
| Pin 72 | I/O — User I/O pin (bank 4) |
| Pin 73 | I/O — User I/O pin (bank 4) |
| Pin 74 | I/O — User I/O pin (bank 4) |
| Pin 75 | I/O — User I/O pin (bank 4) |
| Pin 76 | I/O — User I/O pin (bank 4) |
| Pin 77 | VCCIO4 — I/O supply voltage bank 4 (3.3V or 5V) |
| Pin 78 | I/O — User I/O pin (bank 4) |
| Pin 79 | I/O — User I/O pin (bank 4) |
| Pin 80 | I/O — User I/O pin (bank 4) |
| Pin 81 | I/O — User I/O pin (bank 4) |
| Pin 82 | I/O — User I/O pin (bank 4) |
| Pin 83 | I/O — User I/O pin (bank 4) |
| Pin 84 | I/O — User I/O pin (bank 4) |
| Pin 85 | I/O — User I/O pin (bank 4) |
| Pin 86 | I/O — User I/O pin (bank 4) |
| Pin 87 | GND — Ground |
| Pin 88 | I/O — User I/O pin (bank 5) |
| Pin 89 | I/O — User I/O pin (bank 5) |
| Pin 90 | I/O — User I/O pin (bank 5) |
| Pin 91 | I/O — User I/O pin (bank 5) |
| Pin 92 | I/O — User I/O pin (bank 5) |
| Pin 93 | I/O — User I/O pin (bank 5) |
| Pin 94 | I/O — User I/O pin (bank 5) |
| Pin 95 | I/O — User I/O pin (bank 5) |
| Pin 96 | I/O — User I/O pin (bank 5) |
| Pin 97 | I/O — User I/O pin (bank 5) |
| Pin 98 | I/O — User I/O pin (bank 5) |
| Pin 99 | VCCIO5 — I/O supply voltage bank 5 (3.3V or 5V) |
| Pin 100 | I/O — User I/O pin (bank 5) |
| Pin 101 | I/O — User I/O pin (bank 5) |
| Pin 102 | I/O — User I/O pin (bank 5) |
| Pin 103 | I/O — User I/O pin (bank 5) |
| Pin 104 | I/O — User I/O pin (bank 5) |
| Pin 105 | I/O — User I/O pin (bank 5) |
| Pin 106 | I/O — User I/O pin (bank 5) |
| Pin 107 | I/O — User I/O pin (bank 5) |
| Pin 108 | I/O — User I/O pin (bank 5) |
| Pin 109 | GND — Ground |
| Pin 110 | I/O — User I/O pin (bank 6) |
| Pin 111 | I/O — User I/O pin (bank 6) |
| Pin 112 | I/O — User I/O pin (bank 6) |
| Pin 113 | I/O — User I/O pin (bank 6) |
| Pin 114 | I/O — User I/O pin (bank 6) |
| Pin 115 | I/O — User I/O pin (bank 6) |
| Pin 116 | I/O — User I/O pin (bank 6) |
| Pin 117 | I/O — User I/O pin (bank 6) |
| Pin 118 | I/O — User I/O pin (bank 6) |
| Pin 119 | I/O — User I/O pin (bank 6) |
| Pin 120 | I/O — User I/O pin (bank 6) |
| Pin 121 | VCCIO6 — I/O supply voltage bank 6 (3.3V or 5V) |
| Pin 122 | I/O — User I/O pin (bank 6) |
| Pin 123 | I/O — User I/O pin (bank 6) |
| Pin 124 | I/O — User I/O pin (bank 6) |
| Pin 125 | I/O — User I/O pin (bank 6) |
| Pin 126 | I/O — User I/O pin (bank 6) |
| Pin 127 | I/O — User I/O pin (bank 6) |
| Pin 128 | I/O — User I/O pin (bank 6) |
| Pin 129 | I/O — User I/O pin (bank 6) |
| Pin 130 | I/O — User I/O pin (bank 6) |
| Pin 131 | GND — Ground |
| Pin 132 | I/O — User I/O pin (bank 7) |
| Pin 133 | I/O — User I/O pin (bank 7) |
| Pin 134 | I/O — User I/O pin (bank 7) |
| Pin 135 | I/O — User I/O pin (bank 7) |
| Pin 136 | I/O — User I/O pin (bank 7) |
| Pin 137 | I/O — User I/O pin (bank 7) |
| Pin 138 | I/O — User I/O pin (bank 7) |
| Pin 139 | I/O — User I/O pin (bank 7) |
| Pin 140 | I/O — User I/O pin (bank 7) |
| Pin 141 | I/O — User I/O pin (bank 7) |
| Pin 142 | I/O — User I/O pin (bank 7) |
| Pin 143 | VCCIO7 — I/O supply voltage bank 7 (3.3V or 5V) |
| Pin 144 | I/O — User I/O pin (bank 7) |
| Pin 145 | I/O — User I/O pin (bank 7) |
| Pin 146 | I/O — User I/O pin (bank 7) |
| Pin 147 | I/O — User I/O pin (bank 7) |
| Pin 148 | I/O — User I/O pin (bank 7) |
| Pin 149 | I/O — User I/O pin (bank 7) |
| Pin 150 | I/O — User I/O pin (bank 7) |
| Pin 151 | I/O — User I/O pin (bank 7) |
| Pin 152 | I/O — User I/O pin (bank 7) |
| Pin 153 | GND — Ground |
| Pin 154 | I/O — User I/O pin (bank 8) |
| Pin 155 | I/O — User I/O pin (bank 8) |
| Pin 156 | I/O — User I/O pin (bank 8) |
| Pin 157 | I/O — User I/O pin (bank 8) |
| Pin 158 | I/O — User I/O pin (bank 8) |
| Pin 159 | I/O — User I/O pin (bank 8) |
| Pin 160 | I/O — User I/O pin (bank 8) |
| Pin 161 | I/O — User I/O pin (bank 8) |
| Pin 162 | I/O — User I/O pin (bank 8) |
| Pin 163 | I/O — User I/O pin (bank 8) |
| Pin 164 | I/O — User I/O pin (bank 8) |
| Pin 165 | VCCINT — Internal logic supply voltage (5.0V) |
| Pin 166 | I/O — User I/O pin (bank 8) |
| Pin 167 | I/O — User I/O pin (bank 8) |
| Pin 168 | I/O — User I/O pin (bank 8) |
| Pin 169 | I/O — User I/O pin (bank 8) |
| Pin 170 | I/O — User I/O pin (bank 8) |
| Pin 171 | I/O — User I/O pin (bank 8) |
| Pin 172 | I/O — User I/O pin (bank 8) |
| Pin 173 | I/O — User I/O pin (bank 8) |
| Pin 174 | I/O — User I/O pin (bank 8) |
| Pin 175 | GND — Ground |
| Pin 176 | INPUT/GCLK1 — Global clock input 1 (dedicated) |
| Pin 177 | INPUT/OE1 — Global output enable input 1 (dedicated) |
| Pin 178 | INPUT/GCLRn — Global clear input (dedicated, active low) |
| Pin 179 | TDI — JTAG Test Data In |
| Pin 180 | TMS — JTAG Test Mode Select |
| Pin 181 | TCK — JTAG Test Clock |
| Pin 182 | NC — Not connected (per datasheet) |
| Pin 183 | VCCINT — Internal logic supply voltage (5.0V) |
| Pin 184 | NC — Not connected (per datasheet) |
| Pin 185 | TDO — JTAG Test Data Out |
| Pin 186 | NC — Not connected (per datasheet) |
| Pin 187 | INPUT/OE2 — Global output enable input 2 (dedicated) |
| Pin 188 | INPUT/GCLK2 — Global clock input 2 (dedicated) |
| Pin 189 | I/O — User I/O pin (bank 8) |
| Pin 190 | I/O — User I/O pin (bank 8) |
| Pin 191 | I/O — User I/O pin (bank 8) |
| Pin 192 | I/O — User I/O pin (bank 8) |
| Pin 193 | I/O — User I/O pin (bank 8) |
| Pin 194 | I/O — User I/O pin (bank 8) |
| Pin 195 | I/O — User I/O pin (bank 8) |
| Pin 196 | I/O — User I/O pin (bank 8) |
| Pin 197 | GND — Ground |
| Pin 198 | I/O — User I/O pin (bank 8) |
| Pin 199 | I/O — User I/O pin (bank 8) |
| Pin 200 | I/O — User I/O pin (bank 8) |
| Pin 201 | I/O — User I/O pin (bank 8) |
| Pin 202 | I/O — User I/O pin (bank 8) |
| Pin 203 | I/O — User I/O pin (bank 8) |
| Pin 204 | I/O — User I/O pin (bank 8) |
| Pin 205 | I/O — User I/O pin (bank 8) |
| Pin 206 | I/O — User I/O pin (bank 8) |
| Pin 207 | I/O — User I/O pin (bank 8) |
| Pin 208 | I/O — User I/O pin (bank 8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-19 is suitable for 6 applications: Microprocessor Bus Interface and Glue Logic, State Machine and Control Logic Replacement, Peripheral Control and I/O Expansion, Legacy System Maintenance and Aftermarket, Industrial Automation and Process Control, Telecommunications Backplane and Protocol Bridging.
Microprocessor Bus Interface and Glue Logic
The EPM9560RC208-19's 149 user I/O pins and 560 macrocells make it ideal for microprocessor bus interfacing, address decoding, and chip-select generation in 32-bit and 64-bit systems. Its 19 ns tPD comfortably supports ISA bus timing (8 MHz) and most PCI applications up to 33 MHz when used for decode-only paths. The deterministic PIA routing guarantees consistent timing regardless of logic placement, eliminating the timing closure iterations common with FPGAs.
Recommended
State Machine and Control Logic Replacement
With 772 flip-flops and 560 macrocells, the EPM9560RC208-19 can consolidate dozens of discrete 74-series logic ICs into a single device, simplifying PCB layout and reducing BOM cost. The 19 ns propagation delay supports state-machine clock rates up to approximately 50 MHz, suitable for industrial control sequencers, peripheral controllers, and protocol bridges. The EEPROM-based configuration means instant-on behavior with no boot loader required.
Recommended
Peripheral Control and I/O Expansion
The wide 149-I/O count of the EPM9560RC208-19 in the 208-pin RQFP package is well-suited for I/O expansion in embedded systems where a microcontroller lacks sufficient pins. Designers can implement custom peripheral interfaces such as LCD controllers, key-scan matrices, and parallel-port extenders. The 3.3-V/5-V tolerant I/O enables interfacing with mixed-voltage subsystems without external level shifters.
Recommended
Legacy System Maintenance and Aftermarket
The EPM9560RC208-19 is widely used in legacy industrial, telecommunications, and military systems where PCB redesign is not feasible. Its deterministic timing and proven EEPROM-based reliability make it a trusted component for sustaining field-deployed equipment. Sourcing from authorized distributors and verified brokers is essential due to the part's obsolete lifecycle status.
Recommended
Industrial Automation and Process Control
In industrial automation systems, the EPM9560RC208-19 provides reliable, deterministic logic for PLC I/O modules, motor-control interfaces, and sensor-signal conditioning. Its CMOS EEPROM technology offers excellent noise immunity and stable operation across industrial temperature ranges when ordered with the appropriate -N or -C temperature grade suffix. The JTAG ISP interface enables in-field firmware updates for deployed automation equipment.
Recommended
Telecommunications Backplane and Protocol Bridging
Telecommunications backplanes benefit from the EPM9560RC208-19's deterministic 19 ns timing for protocol bridging between legacy buses such as VME, ISA, and proprietary interfaces. The 149 user I/O pins accommodate wide parallel data paths and control signals. The JTAG ISP enables remote provisioning and field upgrades, valuable for telecom infrastructure with long deployment lifetimes.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-19 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-15 | EPM9560RC208-17 | EPM9560RC208-18 | EPM9560RC208-20 | EPM9560RC208-20C | EPM9560RC208-15N | EPM9560RC208-15C |
|---|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-208 | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same |
| Propagation Delay (tPD) | 19 ns | 15 ns (-21%) | 17 ns (-11%) | 18 ns (-5%) | 20 ns (+5%) | 20 ns (+5%) | 15 ns (-21%) | 15 ns (-21%) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Flip-Flops | 772 | 772 | 772 | 772 | 772 | 772 | 772 | 772 |
| User I/O | 149 | 149 | 149 | 149 | 149 | 149 | 149 | 149 |
| Temperature Grade | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | Commercial | Industrial | Commercial |
Key Differentiators
- Balanced speed-grade positioning within the MAX 9000 family (vs EPM9560RC208-15)
- Same RQFP-208 footprint enables direct substitution (vs EPM9560ARC240-10)
- Wide I/O count of 149 pins for system integration (vs EPM9480RC208-15)
Design Notes
Estimated: at 100 MHz toggle activity on 50% of I/O pins, the EPM9560RC208-19 draws approximately 200-400 mA from VCCINT (5.0 V). Provide at least four 0.1 uF ceramic decoupling capacitors placed adjacent to each VCCINT pin and bulk capacitance on each VCCIO bank. The eight I/O banks can be powered independently at 3.3 V or 5 V, but VCCINT must remain at 5.0 V ±5%.
Do not mix 3.3 V and 5 V signals on the same I/O bank when the bank is configured for 5-V operation - this can damage I/O structures through voltage stress. Ensure JTAG chain integrity by buffering TDI/TDO if multiple devices share the chain. Always issue a bulk erase before reprogramming an EEPROM-based MAX 9000 device to clear any residual configuration bits.
Route high-speed signals (clocks, JTAG) with controlled impedance and keep them short. The RQFP-208 package has lead inductance of approximately 5-7 nH; place decoupling capacitors within 100 mils of each supply pin. Provide a solid ground plane beneath the device for return-current paths and EMI suppression. Exposed-pad variants do not exist for this package - thermal dissipation is through the 208-pin leads.
Compliance Information
Original MAX 9000 family datasheet predates RoHS; specific RoHS compliance not confirmed in available data. Temperature-grade suffix (-N industrial, -C commercial) is the documented ordering code. AEC-Q100 not qualified - this part is not automotive-grade.
