EPM9560RC208-20N vs EPM9560RC208-21 Comparison
Detailed side-by-side comparison of EPM9560RC208-20N by Intel and EPM9560RC208-21 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
EPM9560RC208-21 ⚠ Last Time BuySpecification Comparison
| Parameter | EPM9560RC208-20N | EPM9560RC208-21 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay (tPD) | 20 ns | — |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 149 | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE Std. 1149.1 JTAG) |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Mounting Type | Surface Mount | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial or commercial grade -21 suffix] |
| RoHS Status | Lead-free (N suffix) | [DATA_NEEDED: confirm RoHS compliance for -21 variant] |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | 772 |
| Speed Grade | -20 (20 ns) | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Architecture | — | Multiple Array MatriX (MAX), third-generation |
| Technology | — | CMOS EEPROM-based |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 149 |
| Propagation Delay (speed grade -21) | — | 21 ns (max, per speed grade designation) |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (per variant) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Security Bit | — | Yes (programmable) |