EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
MPN: EPM9560RC208-21 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.75 | $2,975.00 |
| 500 | $26.1 | $13,050.00 |
| 1,000 | $22.95 | $22,950.00 |
Drop-in alternatives for EPM9560RC208-21 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC208-20
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View Datasheet →EPM9560RC208-20N
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View Datasheet →EPM9560RC208-20C
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View Datasheet →EPM9560RC208-15
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View Datasheet →EPM9560RC208-10
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$15.4 / Unit
View Datasheet →EPM9560RC208-21 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX), third-generation |
| Technology | CMOS EEPROM-based |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Flip-Flops | 772 |
| Maximum User I/O | 149 |
| Propagation Delay (speed grade -21) | 21 ns (max, per speed grade designation) |
| Supply Voltage | 5.0 V |
| I/O Voltage Tolerance | 3.3 V or 5 V (per variant) |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| Configuration Memory | EEPROM (non-volatile) |
| Security Bit | Yes (programmable) |
EPM9560RC208-21 208-pin rqfp (power quad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RC208-21 (208-pin rqfp (power quad flat pack) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC208-21.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-21 is suitable for 7 applications: Telecommunication Line-Card Glue Logic, ASIC Prototyping and Pre-Silicon Emulation, Industrial Control and Factory Automation, Microprocessor/Peripheral Bus Address Decoding, Legacy 5 V System Design Refresh, Test and Measurement Instrumentation Backplane, Aerospace and Defense Avionics Retrofit.
Telecommunication Line-Card Glue Logic
The EPM9560RC208-21 is well-suited for legacy telecommunication line-card glue logic because the 560 macrocells and 149 I/O pins can absorb an entire T1/E1 framer interface, an HDLC controller, and address-decoding for a peripheral bus in a single device. The 21 ns propagation delay comfortably meets 33 MHz bus timing, while the non-volatile EEPROM configuration eliminates the boot PROM that would otherwise be required by an FPGA, simplifying the BOM and reducing inrush current. Built-in JTAG ISP enables field upgrades as protocols evolve. Power consumption is dominated by static CMOS current and remains modest even with all 149 I/O switching at 5V.
Recommended
ASIC Prototyping and Pre-Silicon Emulation
For ASIC prototyping, the EPM9560RC208-21's 12,000 usable gates, 772 flip-flops, and 149 I/O make it an ideal vehicle for emulating mid-complexity ASICs before tape-out. Designers can map combinational logic into the 560 macrocells and verify timing closure on real hardware at 33 MHz, well within the 21 ns pin-to-pin budget. The 208-pin RQFP package gives ample I/O for parallel bus probing, and instant-on EEPROM configuration means the prototype is operational at power-up with no external boot logic. Multiple EPM9560RC208-21 devices can be JTAG-chained for larger emulations.
Recommended
Industrial Control and Factory Automation
In factory-automation backplanes, the EPM9560RC208-21 provides deterministic, non-volatile glue logic between PLC backplane buses, sensor interfaces, and actuator drivers. The 21 ns propagation delay is sufficient for 33 MHz deterministic state-machine control, while the high 149 I/O count absorbs wide parallel sensor and relay-driver buses without external muxing. CMOS EEPROM configuration ensures instant-on operation after brown-out events, critical for process-control safety. The RQFP-208 package is industrial-grade with adequate thermal margin in sealed enclosures when derated properly.
Recommended
Microprocessor/Peripheral Bus Address Decoding
The EPM9560RC208-21 excels at multi-master microprocessor address decoding because each of its 560 macrocells handles individual chip-select equations with predictable 21 ns propagation delay. Engineers can decode an entire 32-bit address space plus individual control signals, generate wait-state logic, and arbitrate DMA requests in one device. The non-volatile EEPROM configuration means the decoder is functional at power-on, eliminating the FPGA boot-PROM complexity for a deterministic, instant-on decoding subsystem. JTAG ISP allows last-minute address-map revisions during integration.
Recommended
Legacy 5 V System Design Refresh
For designers maintaining or refreshing legacy 5 V industrial or military systems, the EPM9560RC208-21 remains one of the few high-density programmable logic devices that natively supports 5 V I/O without level shifters. The 560 macrocells and 149 user I/O can replace multiple 22V10 or GAL devices, simplifying the BOM and reducing PCB area. The 208-pin RQFP package is footprint-compatible with all EPM9560 speed grades, enabling last-time-buy safety stock to be deployed flexibly. JTAG ISP simplifies in-field firmware updates without removing the device.
Recommended
Test and Measurement Instrumentation Backplane
In test and measurement instrumentation, the EPM9560RC208-21 functions as the timing-and-control backbone for switching matrices, ADCs, DACs, and trigger logic. The 21 ns propagation delay ensures deterministic timing for precision trigger generation, while 149 I/O handle parallel sample-bus multiplexing and relay-driver arrays. EEPROM configuration provides instant-on boot for instruments that must be operational within milliseconds of power-up, and JTAG ISP supports in-field firmware updates for new measurement algorithms. The RQFP-208 footprint accommodates the dense backplane routing typical of instrument mainboards.
Recommended
Aerospace and Defense Avionics Retrofit
The EPM9560RC208-21's non-volatile EEPROM configuration, deterministic 21 ns timing, and 5 V tolerance make it suitable for avionics retrofit programs where modern FPGAs would require extensive re-qualification. With 560 macrocells and 149 user I/O, a single device can replace multiple legacy PAL/GAL packages while preserving the existing 208-pin RQFP footprint on the avionics PCB. The JTAG ISP interface supports secure field upgrades. Per Altera's discontinuance notice, the 208-pin RQFP package remains in last-time-buy production specifically because defense customers continue to depend on this form-factor.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-21 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-20 | EPM9560RC208-20N | EPM9560RC208-20C | EPM9560RC208-15 | EPM9560RC208-10 |
|---|---|---|---|---|---|---|
| Package | RQFP-208 (Power Quad Flat Pack) | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Propagation Delay (tPD max) | 21 ns | 20 ns (-5%) | 20 ns (-5%) | 20 ns (-5%) | 15 ns (-29%) | 10 ns (-52%) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/O | 149 | 149 | 149 | 149 | 149 | 149 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade | [DATA_NEEDED: -21 grade temperature range] | [DATA_NEEDED] | Commercial (0C to 70C) | Industrial (-40C to +85C) | [DATA_NEEDED] | [DATA_NEEDED] |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
| Unit Price (qty 1, as of 2026-09-13) | $38.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest-density CPLD in the 5 V MAX 9000 family (vs EPM9480RC208-20)
- Instant-on non-volatile configuration with no boot PROM (vs Equivalent FPGA (e.g., Cyclone series))
- True 5 V I/O tolerance on all 149 pins (vs Modern 3.3 V FPGA)
- Deterministic 21 ns pin-to-pin timing (vs FPGA with statistical timing closure)
Design Notes
The EPM9560RC208-21 operates from a single 5.0 V supply and draws Icc that scales with the number of I/O switching simultaneously. Provide at least four dedicated GND pins and four VCC pins (one each on every side of the RQFP-208 package) with low-impedance traces. Decouple each VCC pin with a 0.1 microfarad ceramic capacitor placed within 5 mm of the pin, plus a 10 microfarad tantalum bulk capacitor on each supply rail. Estimated: at 149 I/O toggling at 33 MHz into 50 pF loads, dynamic Icc can reach 300-500 mA in worst-case conditions, requiring the 10 uF bulk capacitor to maintain supply ripple below 100 mV peak-to-peak.
Follow the standard PQFP208 land pattern with 0.5 mm pitch and confirm pad dimensions against the manufacturer package drawing. RQFP packages are gull-wing leaded and tolerate hand-rework better than fine-pitch QFN, but still require careful reflow profile with peak temperature not exceeding 220C for 30 seconds. Provide adequate thermal relief on all VCC and GND pads to balance manufacturability and electrical performance. Keep JTAG TMS, TCK, TDI, TDO traces short (under 50 mm) and isolated from switching I/O to avoid programming errors.
The 21 ns propagation delay budget of the -21 speed grade supports synchronous bus operation up to approximately 33 MHz. For registered outputs, calculate fMAX as 1/(tsu + tco + tPD), where tsu is flip-flop setup time, tco is clock-to-output delay, and tPD is combinational delay. Per the MAX 9000 datasheet, tco is typically 5-8 ns, so fMAX at the speed grade is approximately 35 MHz. Always derive clocks from a low-skew global buffer and avoid distributing clocks through general-purpose I/O to minimize timing skew.
Do not mix the -21 speed grade EPM9560RC208-21 with the -20 or faster grades in the same JTAG chain unless you have unique BSDL files for each device. The -21 suffix encodes both the speed grade and the operating-temperature grade; verify that the -21 ordering code matches your intended commercial vs industrial temperature range before PCB assembly. Per the Altera MAX 9000 datasheet, ISP via JTAG requires 5 V tolerance on TMS, TCK, TDI, TDO pins; do not drive these signals at 3.3 V without a level shifter.
The RQFP-208 package has a typical theta_JA around 30-35 C/W on a standard 4-layer PCB with adequate copper pour. At maximum Icc of approximately 500 mA at 5 V (2.5 W total), junction temperature rise above ambient is approximately 75-88 C, well within the 125 C commercial maximum but a concern in sealed enclosures. Estimated: at 70 C ambient, junction reaches 145-158 C and derating or airflow is required. For industrial or military temperature grades, verify theta_JC and provide a heatsink or copper heat-spreader if the design operates continuously at high I/O toggle rates.
Compliance Information
Compliance status for the EPM9560RC208-21 was not available in the verified web data; engineers should request the latest RoHS/REACH declarations directly from Intel (Altera) for production designs. AEC-Q100 is not applicable because the EPM9560 family is industrial/commercial grade, not automotive qualified.
