EPM9560RC240-15N vs EPM9560RC240-12 Comparison

Detailed side-by-side comparison of EPM9560RC240-15N by Altera and EPM9560RC240-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC240-15N EPM9560RC240-12
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Series MAX 9000 —
Family MAX 9000 (third-generation Multiple Array MatriX) MAX 9000 (EPM9560)
Usable Gates 12,000 —
Macrocells 560 560
Logic Array Blocks (LABs) 35 20
Maximum User I/O Pins 216 —
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Internal Counter Frequency (fCNT) 145 MHz —
Global Setup Time (tFSU) [DATA_NEEDED: tFSU for -15 grade] —
Clock-to-Output Time (tFCO) [DATA_NEEDED: tFCO for -15 grade] —
Supply Voltage 5.0 V —
Logic Family CMOS (EEPROM-based) —
Programmability In-system programmable (IEEE 1532/JTAG) —
Boundary-Scan Test JTAG (IEEE 1149.1) —
Operating Temperature 0C to +70C (Commercial) [DATA_NEEDED: operating temperature grade]
Package RQFP-240 (240-pin Plastic Quad Flat Pack) PQFP-240 (RC240) 0.500 mm pitch, gull-wing
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance - older Altera RQFP part] [DATA_NEEDED: RoHS compliance]
Device Type — EE PLD / CPLD
Flip-Flops — 772
User I/O Pins — 191
Maximum Propagation Delay (tPD) — 13.4 ns
Speed Grade — -12 (13.4 ns tPD)
Maximum Operating Frequency (estimated) — ~76 MHz registered
Core Supply Voltage (VCCINT) — 5 V
I/O Logic Levels — 3.3 V or 5 V (configurable)
Configuration Memory — EEPROM (non-volatile)
Programming Interface — IEEE 1149.1 JTAG
Process Technology — CMOS

Datasheets & Resources

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