EPM9560RC304-10 vs EPM9560RC30415 Comparison
Detailed side-by-side comparison of EPM9560RC304-10 by Intel and EPM9560RC30415 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC304-10 | EPM9560RC30415 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD / EPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | — |
| Usable Gates | 16000 | 12,000 |
| Logic Elements | 560 | — |
| Package | RQFP-304 (RC) | 304-RQFP (Power Quad Flat Pack) |
| Pin Count | 304 | 304 |
| Pin-to-Pin Propagation Delay | 12 ns | — |
| Speed Grade | -10 | -15 (15 ns pin-to-pin delay) |
| Supply Voltage | 5 V | 5.0 V |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| User I/O Pins | 304 (package-limited) | 360 |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Programming Method | JTAG in-system (ISP) | — |
| Process Technology | 0.65 µm CMOS EEPROM | — |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | 3 (168 Hours) | — |
| RoHS Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Architecture | — | Multiple Array MatriX (MAX), EEPROM-based |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 (40 macro cells each) |
| Maximum Internal Frequency | — | 117.6 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Technology | — | CMOS EEPROM |