EPM9560RC304-20N vs EPM9560RI304 Comparison
Detailed side-by-side comparison of EPM9560RC304-20N by Altera and EPM9560RI304 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC304-20N | EPM9560RI304 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 20 | — |
| User I/O Pins | 212 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum System Frequency | 100 MHz | — |
| Core Supply Voltage | 5.0 V | — |
| I/O Voltage Support | 3.3 V or 5.0 V configurable | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Package | 304-pin RQFP (PowerQuad) | 304-pin BFQFP/RQFP (HFQFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | RoHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | — |
| Manufacturer Standard Lead Time | 1-7 Days (distributor listing) | — |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Maximum User I/O Pins | — | 216 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (JTAG) |
| Package Code | — | HFQFP, square |
| Terminal Form | — | Gull wing |
| Number of Terminals | — | 304 |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Architecture | — | Multiple Array MatriX (MAX) with Logic Array Blocks and Programmable Interconnect Array |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |