EPM9560RC304-20N vs EPM9560RI304 对比

详细并排对比 EPM9560RC304-20N 出自 Altera 和 EPM9560RI304 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC304-20N EPM9560RI304
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $0.00
Device Family MAX 9000 (EPM9560) MAX 9000
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 20 —
User I/O Pins 212 —
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) —
Maximum System Frequency 100 MHz —
Core Supply Voltage 5.0 V —
I/O Voltage Support 3.3 V or 5.0 V configurable —
Configuration Technology EEPROM (non-volatile, in-system programmable) —
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
封装 304-pin RQFP (PowerQuad) 304-pin BFQFP/RQFP (HFQFP)
安装类型 Surface Mount Surface Mount
工作温度范围 [DATA_NEEDED: operating temperature range] —
RoHS 状态 RoHS3 Compliant [DATA_NEEDED: RoHS status]
湿敏等级(MSL) 3 (168 Hours) —
Manufacturer Standard Lead Time 1-7 Days (distributor listing) —
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Maximum User I/O Pins — 216
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Configuration Memory — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface — IEEE Std. 1149.1 (JTAG)
Package Code — HFQFP, square
Terminal Form — Gull wing
Number of Terminals — 304
Operating Temperature Grade — Industrial (-40C to +85C)
Architecture — Multiple Array MatriX (MAX) with Logic Array Blocks and Programmable Interconnect Array
Lead-Free Status — [DATA_NEEDED: lead-free status]

数据手册与资源

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