EPM9560RI208-15N vs EPM9400RC208-20 Comparison

Detailed side-by-side comparison of EPM9560RI208-15N by Altera and EPM9400RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RI208-15N EPM9400RC208-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Manufacturer Altera (Intel Programmable Solutions Group) —
Device Family MAX 9000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX), 3rd generation —
Configuration Memory CMOS EEPROM, in-system programmable —
Package 208-pin RQFP (Ruggedized Quad Flat Pack) 208-pin RQFP (28x28 mm)
Total Pins 356 (per third-party catalog; see _validation_note) —
Package Pin Count 208 —
Terminal Form Gull Wing —
Package Code HFQFP —
User I/Os 216 (per DigiChip specification; see _validation_note) —
Maximum Internal Frequency 145 MHz —
Propagation Delay (tPD) 11.4 ns (15 ns speed grade) —
Speed Grade -15 -20 (20 ns)
Supply Voltage 5.0 V —
Operating Temperature 0C to 70C (Commercial) [DATA_NEEDED: operating temperature range]
Temperature Grade Industrial (per Vyrian/Partstack listings) —
Logic Family CMOS —
Programming Interface IEEE 1149.1 JTAG, 5.0-V in-system —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Family — MAX 9000
Programmable Type — In System Programmable (ISP)
Macro Cells — 400
Usable Gates — 8,000
Pin-to-Pin Propagation Delay — 20 ns
Maximum Operating Frequency — 100 MHz
Supply Voltage (Internal) — 4.75 V to 5.25 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Supplier Device Package — 208-RQFP
Mounting Type — Surface Mount
Number of I/O Pins — [DATA_NEEDED: user I/O count]
MSL Level — [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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