EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
MPN: EPM9560RI208-15N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $27.85 | $2,785.00 |
| 500 | $23.1 | $11,550.00 |
| 1,000 | $19.45 | $19,450.00 |
Drop-in alternatives for EPM9560RI208-15N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM9560RI208-15N Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (Intel Programmable Solutions Group) |
| Device Family | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| Configuration Memory | CMOS EEPROM, in-system programmable |
| Package | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Total Pins | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | 208 |
| Terminal Form | Gull Wing |
| Package Code | HFQFP |
| User I/Os | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | 145 MHz |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) |
| Speed Grade | -15 |
| Supply Voltage | 5.0 V |
| Operating Temperature | 0C to 70C (Commercial) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) |
| Logic Family | CMOS |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system |
EPM9560RI208-15N Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | VCC — 5.0 V supply |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | VCC — 5.0 V supply |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | VCC — 5.0 V supply |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | VCC — 5.0 V supply |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | GND — Ground |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | VCC — 5.0 V supply |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | VCC — 5.0 V supply |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | GND — Ground |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | VCC — 5.0 V supply |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | VCC — 5.0 V supply |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | GND — Ground |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | VCC — 5.0 V supply |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | VCC — 5.0 V supply |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
| Pin 101 | GND — Ground |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 107 | TMS — JTAG Test Mode Select |
| Pin 108 | TCK — JTAG Test Clock |
| Pin 109 | TDO — JTAG Test Data Out |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | GND — Ground |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | VCC — 5.0 V supply |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | GND — Ground |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | VCC — 5.0 V supply |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | GND — Ground |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | VCC — 5.0 V supply |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | I/O — User I/O pin |
| Pin 141 | GND — Ground |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
| Pin 145 | I/O — User I/O pin |
| Pin 146 | VCC — 5.0 V supply |
| Pin 147 | I/O — User I/O pin |
| Pin 148 | I/O — User I/O pin |
| Pin 149 | I/O — User I/O pin |
| Pin 150 | I/O — User I/O pin |
| Pin 151 | GND — Ground |
| Pin 152 | I/O — User I/O pin |
| Pin 153 | I/O — User I/O pin |
| Pin 154 | I/O — User I/O pin |
| Pin 155 | I/O — User I/O pin |
| Pin 156 | VCC — 5.0 V supply |
| Pin 157 | I/O — User I/O pin |
| Pin 158 | I/O — User I/O pin |
| Pin 159 | I/O — User I/O pin |
| Pin 160 | I/O — User I/O pin |
| Pin 161 | GND — Ground |
| Pin 162 | I/O — User I/O pin |
| Pin 163 | I/O — User I/O pin |
| Pin 164 | I/O — User I/O pin |
| Pin 165 | I/O — User I/O pin |
| Pin 166 | VCC — 5.0 V supply |
| Pin 167 | I/O — User I/O pin |
| Pin 168 | I/O — User I/O pin |
| Pin 169 | I/O — User I/O pin |
| Pin 170 | I/O — User I/O pin |
| Pin 171 | GND — Ground |
| Pin 172 | I/O — User I/O pin |
| Pin 173 | I/O — User I/O pin |
| Pin 174 | I/O — User I/O pin |
| Pin 175 | I/O — User I/O pin |
| Pin 176 | VCC — 5.0 V supply |
| Pin 177 | I/O — User I/O pin |
| Pin 178 | I/O — User I/O pin |
| Pin 179 | I/O — User I/O pin |
| Pin 180 | I/O — User I/O pin |
| Pin 181 | GND — Ground |
| Pin 182 | I/O — User I/O pin |
| Pin 183 | I/O — User I/O pin |
| Pin 184 | I/O — User I/O pin |
| Pin 185 | I/O — User I/O pin |
| Pin 186 | VCC — 5.0 V supply |
| Pin 187 | I/O — User I/O pin |
| Pin 188 | I/O — User I/O pin |
| Pin 189 | I/O — User I/O pin |
| Pin 190 | I/O — User I/O pin |
| Pin 191 | GND — Ground |
| Pin 192 | I/O — User I/O pin |
| Pin 193 | I/O — User I/O pin |
| Pin 194 | I/O — User I/O pin |
| Pin 195 | I/O — User I/O pin |
| Pin 196 | VCC — 5.0 V supply |
| Pin 197 | I/O — User I/O pin |
| Pin 198 | I/O — User I/O pin |
| Pin 199 | I/O — User I/O pin |
| Pin 200 | I/O — User I/O pin |
| Pin 201 | GND — Ground |
| Pin 202 | I/O — User I/O pin |
| Pin 203 | I/O — User I/O pin |
| Pin 204 | I/O — User I/O pin |
| Pin 205 | I/O — User I/O pin |
| Pin 206 | VCC — 5.0 V supply |
| Pin 207 | I/O — User I/O pin |
| Pin 208 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI208-15N is suitable for 6 applications: 32-bit/64-bit Microprocessor Glue Logic, PCI / ISA / VME Bus Interface Bridging, Industrial Control and Factory Automation, Legacy Telecom Backplane Logic, High-Density State Machine Controllers, Military / Aerospace Avionics Databuses.
32-bit/64-bit Microprocessor Glue Logic
The EPM9560RI208-15N fits 32-bit and 64-bit microprocessor glue-logic designs thanks to its 216 user I/Os and 12,000 usable gates in the MAX 9000 architecture, which is sufficient to integrate address decoding, wait-state generation, and chip-select logic for an entire system. The 11.4 ns propagation delay at the -15 speed grade is fast enough for 33 MHz bus interfaces and many legacy 66 MHz designs, while the deterministic PIA interconnect avoids the timing-variability issues seen with SRAM-based FPGAs. Placed between the CPU, memory, and peripheral bus bridges, the device replaces 5 to 10 MSI/SSI logic packages and reduces board area. Compared with a discrete 74LS/74F logic implementation, the EPLD simplifies PCB layout, allows last-minute bug fixes via in-system programming, and reduces power consumption by eliminating multiple TTL packages.
Recommended
PCI / ISA / VME Bus Interface Bridging
The EPM9560RI208-15N is well suited to PCI, ISA, and VME bus interface bridging where its 5.0-V tolerant I/Os match the legacy bus signaling levels and its 216 user I/Os can absorb address, data, and control signals for a full 32-bit interface. The 11.4 ns propagation delay combined with the deterministic MAX 9000 interconnect makes timing closure achievable for 33 MHz PCI without manual delay-line tuning. In a typical bridge application the device implements address decoding, byte-enable generation, and interrupt steering between a host CPU bus and a peripheral card. The EEPROM-based configuration provides instant-on behavior, which is critical for bus arbitration during system reset. Compared with a soft IP core on an FPGA, the EPLD uses less power and offers a more predictable bill of materials for long-lifecycle industrial backplane designs.
Recommended
Industrial Control and Factory Automation
The EPM9560RI208-15N fits industrial control and factory automation designs that need a deterministic, reprogrammable logic device with the industrial temperature grade offered by the N-suffix screening. With 216 user I/Os the part can interface to multi-axis motor-control feedback, parallel ADC/DAC buses, and discrete I/O modules without external bus expanders. The 11.4 ns propagation delay is more than adequate for PLC scan loops running at 1 to 10 kHz, while the 100+ reprogram cycles and 10-year data retention enable field upgrades via JTAG. Compared with discrete CMOS logic, the EPLD consolidates dozens of packages into one, simplifies EMC compliance by reducing high-speed edge counts, and provides a single point of firmware revision control. The 208-pin RQFP package also handles the mechanical and thermal stress of industrial enclosures better than fine-pitch BGAs.
Recommended
Legacy Telecom Backplane Logic
The EPM9560RI208-15N supports legacy telecom backplane designs where T1/E1 framers, channel-associated signalling chips, and switch-fabric controllers require a high-I/O programmable glue layer. The 5.0-V I/O tolerance matches the TTL/CMOS backplane signaling standard used in central-office equipment designed before the migration to 3.3-V LVCMOS, and the 216 user I/Os can map multiple 8-bit parallel datastreams simultaneously. The deterministic 11.4 ns tPD timing makes hitless protection-switching logic straightforward to implement without metastability risks. Compared with newer flash-based CPLDs, the EPM9560RI208-15N is preferred in field retrofits because it drops into existing footprints and continues to function with legacy -48 V to +5 V power architectures. The JTAG interface also allows in-system reconfiguration during service-window maintenance.
Recommended
High-Density State Machine Controllers
The EPM9560RI208-15N is an excellent fit for high-density state-machine controllers in test, measurement, and instrumentation equipment. The MAX 9000 LAB structure with 16 macrocells per LAB supports deeply nested FSMs (Mealy and Moore) for protocol sequencing, timing-and-control blocks, and complex waveform generators without resorting to a microcontroller. The 11.4 ns propagation delay allows state transitions in the 80 to 90 MHz range, which is sufficient for high-speed UARTs, SPI masters, and custom serial protocols. Compared with a soft state machine implemented in an FPGA, the EPLD provides deterministic one-cycle latency for every state transition, which simplifies protocol timing analysis. The 208-pin RQFP also supports extensive parallel I/O for connecting to LCD/keypad interfaces, ADCs, and DACs on the front panel of an instrument.
Recommended
Military / Aerospace Avionics Databuses
The EPM9560RI208-15N is suitable for military and aerospace avionics databus interfaces such as MIL-STD-1553, ARINC 429, and RS-422/485 channel aggregation, where its 216 user I/Os can buffer and route multiple channels simultaneously. The deterministic MAX 9000 interconnect and 11.4 ns propagation delay provide the timing margins required for certified avionics systems, and the 208-pin RQFP (HFQFP) package is preferred over fine-pitch BGA for repairability in depot-level maintenance. Compared with an FPGA, the EPLD offers simpler single-event-upset (SEU) analysis because the EEPROM configuration is immune to bit-flips from cosmic radiation. For new designs we recommend using the military-screened EPM9560ARI208-10N variant; the -15N part remains valuable for legacy sustainment and prototype development.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI208-15N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-10N | EPM9560RI208-10 | EPM9480RC208-15N | EPM9320RI208-20N |
|---|---|---|---|---|---|
| Package | 208-pin RQFP (HFQFP) | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Usable Gates | 12,000 | 12,000 | 10,000 (-17%) | 8,000 (-33%) | 6,000 (-50%) |
| Speed Grade (tPD) | 11.4 ns (-15) | 10 ns (-10) | 11.4 ns (-15) | 20 ns (-20) | 20 ns (-20) |
| Internal Frequency | 145 MHz | 167 MHz | 145 MHz | 125 MHz | 125 MHz |
| Temperature Grade | Industrial (0C to 70C) | Commercial | Industrial | Commercial | Industrial |
| User I/Os (typical) | 216 | 216 | 212 | 204 | 196 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. 100-pc Price (USD) | $27.85 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest gate density in the MAX 9000 family at the -15 speed grade (vs EPM9480RC208-15N)
- Faster tPD than EPM9400/EPM9320 at the same package (vs EPM9320RI208-20N)
- Industrial temperature screening for harsh environments (vs EPM9560RI208-10 (no N suffix))
Design Notes
Estimated: The EPM9560RI208-15N draws approximately 200 to 300 mA quiescent supply current at 5.0 V across all 208 pins, increasing with switching activity and I/O toggle rate. We recommend placing one 0.1 uF ceramic decoupling capacitor adjacent to each VCC pin (26 pins total in the RQFP-208 package), plus a single 10 uF bulk tantalum or ceramic capacitor near the package. Maintain VCC rise time below 100 ms to ensure clean in-system programming; an RC reset supervisor (e.g. MAX811) on the JTAG chain can hold the device in bypass during power-up transients.
The 208-pin RQFP (28 x 28 mm body, 0.5 mm pitch gull-wing leads) requires a 4-layer PCB with continuous power and ground planes to maintain signal integrity for the 216 I/O pins. Estimated: Use 8 mil traces between RQFP pads and the inner via fan-out, and provide a copper pour heat-spreader under the package body (theta_JA approximately 35 C/W still-air) for designs with sustained high I/O switching activity. Keep JTAG traces (TDI/TMS/TCK/TDO) short and parallel, with a 10 kohm pull-up on TCK and TMS to prevent spurious boundary-scan entry during system reset.
Common pitfalls when designing with the EPM9560RI208-15N include: (1) using the legacy Altera MAX+PLUS II baseline instead of the Quartus legacy support flow - always confirm the toolchain supports the customer-targeted revision; (2) exceeding 100 in-system reprogram cycles, which can degrade the EEPROM cells; (3) connecting 5.0-V tolerant I/Os to 3.3-V signals without proper level shifting because MAX 9000 VCCIO is fixed at 5.0 V; (4) omitting the IEEE 1149.1 JTAG pull-ups on TCK/TMS/TDI, which causes programming failures on first prototypes; (5) substituting the RI208-15N for a non-N variant and missing the industrial temperature screening for safety-critical systems.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status not provided in the verified web data; MAX 9000 family is generally not AEC-Q100 qualified (choose EPM9560ARI208-10N for MIL-PRF screening). Compliance values marked [DATA_NEEDED].
