EPM9560RI240-15N vs EPM9560RC240-10N Comparison
Detailed side-by-side comparison of EPM9560RI240-15N by Intel and EPM9560RC240-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RI240-15N
EPM9560RI240-15N - MAX 9000 CPLD 560 Macrocell | Intel
EPM9560RI240-15N ObsoleteIntel
EPM9560RC240-10N
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N β Last Time BuySpecification Comparison
| Parameter | EPM9560RI240-15N | EPM9560RC240-10N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $168.00 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Logic Family | MAX 9000 (Multiple Array MatriX) | β |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | β |
| Usable Gates | 12,000 | 12,000 |
| User I/O Pins | 216 | β |
| Package | 240-pin RQFP (PowerQuad Flat Pack) | 240-pin RQFP (Plastic Quad Flat Pack) |
| Pin-to-Pin Propagation Delay | 15 ns | β |
| Internal Frequency | 145 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5.0 V configurable | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | β |
| JTAG Interface | IEEE 1149.1 (JTAG) boundary scan | β |
| Operating Temperature Range | -40 C to +85 C (industrial) | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | RoHS3 Compliant | ROHS3 Compliant (per fpgalink.com listing) |
| Moisture Sensitivity Level | MSL 3 (168 hours) | β |
| Manufacturer Standard Lead Time | 1-7 days (distributor stock) | β |
| Family | β | MAX 9000 |
| Architecture | β | Multiple Array MatriX (MAX) - 3rd generation |
| Logic Array Blocks (LABs) | β | 16 |
| User I/Os | β | 212 |
| Internal Operating Frequency | β | 144.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | β | 10 ns (-10 speed grade) |
| Process Technology | β | 0.65 Β΅m CMOS EEPROM |
| Programming Interface | β | JTAG (IEEE 1149.1) - in-system programmable |
| I/O Standards Supported | β | 5.0 V TTL/CMOS, 3.3 V PCI-compatible |
| Operating Temperature (Commercial) | β | 0 Β°C to +70 Β°C |
| Lead-Free Finish (N suffix) | β | Yes (Pb-free) |
| Moisture Sensitivity Level (MSL) | β | 3 (168 hours) |