EPM9560RI240-15N vs EPM9560RC240-10N Vergleich
Detaillierter Direktvergleich von EPM9560RI240-15N von Intel und EPM9560RC240-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9560RI240-15N | EPM9560RC240-10N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $168,00 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Logic Family | MAX 9000 (Multiple Array MatriX) | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| Usable Gates | 12,000 | 12,000 |
| User I/O Pins | 216 | — |
| Gehäuse | 240-pin RQFP (PowerQuad Flat Pack) | 240-pin RQFP (Plastic Quad Flat Pack) |
| Pin-to-Pin Propagation Delay | 15 ns | — |
| Internal Frequency | 145 MHz | — |
| Versorgungsspannung | 5.0 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5.0 V configurable | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE 1149.1 (JTAG) boundary scan | — |
| Betriebstemperaturbereich | -40 C to +85 C (industrial) | — |
| Montageart | Surface Mount | — |
| RoHS-Status | RoHS3 Compliant | ROHS3 Compliant (per fpgalink.com listing) |
| Moisture Sensitivity Level | MSL 3 (168 hours) | — |
| Manufacturer Standard Lead Time | 1-7 days (distributor stock) | — |
| Family | — | MAX 9000 |
| Architecture | — | Multiple Array MatriX (MAX) - 3rd generation |
| Logic Array Blocks (LABs) | — | 16 |
| User I/Os | — | 212 |
| Internal Operating Frequency | — | 144.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Process Technology | — | 0.65 µm CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) - in-system programmable |
| I/O Standards Supported | — | 5.0 V TTL/CMOS, 3.3 V PCI-compatible |
| Operating Temperature (Commercial) | — | 0 °C to +70 °C |
| Lead-Free Finish (N suffix) | — | Yes (Pb-free) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | — | 3 (168 hours) |