EPM9560RI240-20 vs EPM9560RI240-20N Comparison
Detailed side-by-side comparison of EPM9560RI240-20 by Altera and EPM9560RI240-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RI240-20
EPM9560RI240-20 - MAX 9000 CPLD 560 Macro 191 IO | Altera
EPM9560RI240-20 NrndIntel
EPM9560RI240-20N
EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel
EPM9560RI240-20N β Last Time BuySpecification Comparison
| Parameter | EPM9560RI240-20 | EPM9560RI240-20N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $195.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 560 | 560 |
| User I/O Pins | 191 | β |
| Pin-to-Pin Propagation Delay | 20 ns | β |
| Supply Voltage | 5.0 V | β |
| Configuration Technology | CMOS EEPROM (non-volatile) | β |
| In-System Programmability | Yes (ISP) | β |
| Package | 240-pin RQFP (PowerQuad II) with exposed pad | 240-pin Power-enhanced BGA (RI240) |
| Mounting Type | Surface Mount | β |
| Operating Temperature Range | Industrial (-40C to +85C) | β |
| Logic Gates | 10,000 | β |
| Internal Frequency | [DATA_NEEDED: internal frequency] | β |
| Number of Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| REACH Status | Compliant (per Abacus Technologies listing) | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Packaging | Tray | β |
| Architecture | β | Multiple Array MatriX (MAX) - third generation |
| Logic Array Blocks (LABs) | β | 12 |
| User I/Os | β | 191 |
| Maximum Internal Frequency | β | 145 MHz |
| Pin-to-Pin Propagation Delay (tPD) | β | 11.4 ns |
| Logic Family | β | CMOS |
| Process Technology | β | CMOS EEPROM |
| Programmability | β | In-system programmable (ISP) via JTAG (IEEE 1149.1) |
| Core Supply Voltage | β | 5.0 V |
| MultiVolt I/O | β | 5.0 V / 3.3 V compatible |
| Operating Temperature | β | 0C to +70C (commercial) |
| Programming Language Support | β | AHDL, VHDL, Verilog HDL |
| Development Tools | β | MAX+PLUS II, Quartus II |