EPM9560SRC208-7 vs EPM9560RC208-7 Comparison
Detailed side-by-side comparison of EPM9560SRC208-7 by Altera and EPM9560RC208-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560SRC208-7 | EPM9560RC208-7 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD / CPLD |
| Usable Gates | 12,000 | 560 |
| Macrocells | 560 | 16 |
| Logic Array Blocks (LABs) | 16 | 4 |
| Maximum I/O Pins | 212 | — |
| Package | 208-pin SQFP (Surface-mount Quad Flat Pack) | 208-pin Power Quad Flat Pack (RQFP-208) |
| Pin-to-Pin Logic Delay (tPD) | 7.0 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT for -7 speed grade] | — |
| Supply Voltage (VCC) | 5.0 V (single supply) | — |
| Programming Method | In-system via IEEE Std 1149.1 JTAG | — |
| Operating Temperature Range | -40 °C to +85 °C (industrial) | — |
| Technology | CMOS, EEPROM-based | — |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: per part marking / distributor listing] | Compliant (ROHS3 per distributor listing) |
| MSL Level | [DATA_NEEDED: not stated in mature datasheet] | — |
| User I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 7 ns (speed grade -7) |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Supply Voltage (VCCIO) | — | 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) |
| Process Technology | — | 0.65 um CMOS EEPROM |
| Configuration Memory | — | Non-volatile on-chip EEPROM (no boot PROM required) |
| Programming Interface | — | JTAG (IEEE 1149.1) + Altera ISP |
| Operating Temperature | — | 0C to +70C (commercial) / -40C to +85C (industrial) |
| Output Drive Current | — | 160 mA DC sink per pin |