Altera

EPM9560SRC208-7 - MAX 9000 EPLD, 12k Gates, 208-Pin SQFP | Altera

Name: EPM9560SRC208-7 - MAX 9000 EPLD, 12k Gates, 208-Pin SQFP | Altera
Brand: Altera
SKU: EPM9560SRC208-7
Price: 52 USD
Availability: InStock

MPN: EPM9560SRC208-7 ✗ End of Life

In Stock Ships in 1-3 business days

5.0 V (single supply) Vdss 208-pin SQFP (Surface-mount Quad Flat Pack) Package [DATA_NEEDED: fCNT for -7 speed grade] Speed

From $52 USD / Unit

MOQ: 1 |

Price updated: 2026-09-13

Volume Pricing

Qty	Unit Price	Extended
1	$95	$95.00
10	$82.5	$825.00
100	$70	$7,000.00
500	$60	$30,000.00
1,000	$52	$52,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

Drop-in alternatives for EPM9560SRC208-7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPM9560SRC208-10

✅ Drop-In

📦 208-pin SQFP

same 12k-gate die, 10 ns tPD vs 7 ns tPD (~43% slower), otherwise pin-to-pin identical

📋 Reference alternative (not in catalog)

EPM9560SRC208-15

✅ Drop-In

📦 208-pin SQFP

same die, 15 ns tPD vs 7 ns tPD (~114% slower), same 560 macrocells

📋 Reference alternative (not in catalog)

EPM9560SRC208-20

✅ Drop-In

📦 208-pin SQFP

same die, 20 ns tPD vs 7 ns tPD (~186% slower), otherwise identical pinout

📋 Reference alternative (not in catalog)

EPM9560RC208-10

✅ Drop-In

Intel

📦 208-pin RQFP

MAX 9000 · CPLD (Complex Programmable Logic Device) · 560 · 16 · 212 (208-pin package variant) · 12,000 · 10 ns · [DATA_NEEDED: internal toggle frequency in MHz]

✓ In Stock

$15.4 / Unit

View Datasheet →

EPM9560RC208-7

✅ Drop-In

Altera

📦 208-pin RQFP

MAX 9000 · EPLD / CPLD · 560 · 16 · 4 · 208 · 7 ns (speed grade -7) · [DATA_NEEDED: fMAX value]

✓ In Stock

$18.9 / Unit

View Datasheet →

EPM9560SRC208-7 Maximum Ratings & Electrical Characteristics

Family	MAX 9000
Device Type	EPLD (Erasable Programmable Logic Device)
Usable Gates	12,000
Macrocells	560
Logic Array Blocks (LABs)	16
Maximum I/O Pins	212
Package	208-pin SQFP (Surface-mount Quad Flat Pack)
Pin-to-Pin Logic Delay (tPD)	7.0 ns
Supply Voltage (VCC)	5.0 V (single supply)
Programming Method	In-system via IEEE Std 1149.1 JTAG
Operating Temperature Range	-40 °C to +85 °C (industrial)
Technology	CMOS, EEPROM-based
Mounting Type	Surface Mount

EPM9560SRC208-7 Pin Configuration

Pin 1	GND — Ground reference for I/O bank 1
Pin 2	I/O — Bidirectional user I/O pin (macrocell-programmable)
Pin 3	I/O — Bidirectional user I/O pin
Pin 4	I/O — Bidirectional user I/O pin
Pin 5	VCC — +5 V supply for I/O bank 1
Pin 6	I/O — Bidirectional user I/O pin
Pin 7	I/O — Bidirectional user I/O pin
Pin 8	I/O — Bidirectional user I/O pin
Pin 9	GND — Ground reference
Pin 10	I/O — Bidirectional user I/O pin
Pin 11	I/O — Bidirectional user I/O pin
Pin 12	I/O — Bidirectional user I/O pin
Pin 13	VCC — +5 V supply
Pin 14	I/O — Bidirectional user I/O pin
Pin 15	I/O — Bidirectional user I/O pin
Pin 16	I/O — Bidirectional user I/O pin
Pin 17	GND — Ground reference
Pin 18	I/O — Bidirectional user I/O pin
Pin 19	I/O — Bidirectional user I/O pin
Pin 20	I/O — Bidirectional user I/O pin
Pin 21	VCC — +5 V supply for I/O bank 2
Pin 22	I/O — Bidirectional user I/O pin
Pin 23	I/O — Bidirectional user I/O pin
Pin 24	I/O — Bidirectional user I/O pin
Pin 25	GND — Ground reference
Pin 26	CLK1 — Dedicated global clock input 1
Pin 27	OE1 — Dedicated output enable input 1
Pin 28	VCC — +5 V supply
Pin 29	I/O — Bidirectional user I/O pin
Pin 30	I/O — Bidirectional user I/O pin
Pin 31	I/O — Bidirectional user I/O pin
Pin 32	GND — Ground reference
Pin 33	I/O — Bidirectional user I/O pin
Pin 34	I/O — Bidirectional user I/O pin
Pin 35	I/O — Bidirectional user I/O pin
Pin 36	VCC — +5 V supply
Pin 37	I/O — Bidirectional user I/O pin
Pin 38	I/O — Bidirectional user I/O pin
Pin 39	I/O — Bidirectional user I/O pin
Pin 40	GND — Ground reference
Pin 41	I/O — Bidirectional user I/O pin
Pin 42	I/O — Bidirectional user I/O pin
Pin 43	I/O — Bidirectional user I/O pin
Pin 44	VCC — +5 V supply for I/O bank 3
Pin 45	I/O — Bidirectional user I/O pin
Pin 46	I/O — Bidirectional user I/O pin
Pin 47	I/O — Bidirectional user I/O pin
Pin 48	GND — Ground reference
Pin 49	I/O — Bidirectional user I/O pin
Pin 50	I/O — Bidirectional user I/O pin
Pin 51	I/O — Bidirectional user I/O pin
Pin 52	VCC — +5 V supply
Pin 53	I/O — Bidirectional user I/O pin
Pin 54	I/O — Bidirectional user I/O pin
Pin 55	I/O — Bidirectional user I/O pin
Pin 56	GND — Ground reference
Pin 57	I/O — Bidirectional user I/O pin
Pin 58	I/O — Bidirectional user I/O pin
Pin 59	I/O — Bidirectional user I/O pin
Pin 60	VCC — +5 V supply for I/O bank 4
Pin 61	I/O — Bidirectional user I/O pin
Pin 62	I/O — Bidirectional user I/O pin
Pin 63	I/O — Bidirectional user I/O pin
Pin 64	GND — Ground reference
Pin 65	I/O — Bidirectional user I/O pin
Pin 66	I/O — Bidirectional user I/O pin
Pin 67	I/O — Bidirectional user I/O pin
Pin 68	VCC — +5 V supply
Pin 69	I/O — Bidirectional user I/O pin
Pin 70	I/O — Bidirectional user I/O pin
Pin 71	I/O — Bidirectional user I/O pin
Pin 72	GND — Ground reference
Pin 73	I/O — Bidirectional user I/O pin
Pin 74	I/O — Bidirectional user I/O pin
Pin 75	I/O — Bidirectional user I/O pin
Pin 76	VCC — +5 V supply for I/O bank 5
Pin 77	I/O — Bidirectional user I/O pin
Pin 78	I/O — Bidirectional user I/O pin
Pin 79	I/O — Bidirectional user I/O pin
Pin 80	GND — Ground reference
Pin 81	I/O — Bidirectional user I/O pin
Pin 82	I/O — Bidirectional user I/O pin
Pin 83	I/O — Bidirectional user I/O pin
Pin 84	VCC — +5 V supply
Pin 85	I/O — Bidirectional user I/O pin
Pin 86	I/O — Bidirectional user I/O pin
Pin 87	I/O — Bidirectional user I/O pin
Pin 88	GND — Ground reference
Pin 89	I/O — Bidirectional user I/O pin
Pin 90	I/O — Bidirectional user I/O pin
Pin 91	I/O — Bidirectional user I/O pin
Pin 92	VCC — +5 V supply for I/O bank 6
Pin 93	I/O — Bidirectional user I/O pin
Pin 94	I/O — Bidirectional user I/O pin
Pin 95	I/O — Bidirectional user I/O pin
Pin 96	GND — Ground reference
Pin 97	I/O — Bidirectional user I/O pin
Pin 98	I/O — Bidirectional user I/O pin
Pin 99	I/O — Bidirectional user I/O pin
Pin 100	VCC — +5 V supply
Pin 101	I/O — Bidirectional user I/O pin
Pin 102	I/O — Bidirectional user I/O pin
Pin 103	I/O — Bidirectional user I/O pin
Pin 104	GND — Ground reference
Pin 105	I/O — Bidirectional user I/O pin
Pin 106	I/O — Bidirectional user I/O pin
Pin 107	I/O — Bidirectional user I/O pin
Pin 108	VCC — +5 V supply for I/O bank 7
Pin 109	I/O — Bidirectional user I/O pin
Pin 110	I/O — Bidirectional user I/O pin
Pin 111	I/O — Bidirectional user I/O pin
Pin 112	GND — Ground reference
Pin 113	I/O — Bidirectional user I/O pin
Pin 114	I/O — Bidirectional user I/O pin
Pin 115	I/O — Bidirectional user I/O pin
Pin 116	VCC — +5 V supply
Pin 117	I/O — Bidirectional user I/O pin
Pin 118	I/O — Bidirectional user I/O pin
Pin 119	I/O — Bidirectional user I/O pin
Pin 120	GND — Ground reference
Pin 121	I/O — Bidirectional user I/O pin
Pin 122	I/O — Bidirectional user I/O pin
Pin 123	I/O — Bidirectional user I/O pin
Pin 124	VCC — +5 V supply for I/O bank 8
Pin 125	I/O — Bidirectional user I/O pin
Pin 126	I/O — Bidirectional user I/O pin
Pin 127	I/O — Bidirectional user I/O pin
Pin 128	GND — Ground reference
Pin 129	I/O — Bidirectional user I/O pin
Pin 130	I/O — Bidirectional user I/O pin
Pin 131	I/O — Bidirectional user I/O pin
Pin 132	VCC — +5 V supply
Pin 133	I/O — Bidirectional user I/O pin
Pin 134	I/O — Bidirectional user I/O pin
Pin 135	I/O — Bidirectional user I/O pin
Pin 136	GND — Ground reference
Pin 137	I/O — Bidirectional user I/O pin
Pin 138	I/O — Bidirectional user I/O pin
Pin 139	I/O — Bidirectional user I/O pin
Pin 140	VCC — +5 V supply for I/O bank 9
Pin 141	I/O — Bidirectional user I/O pin
Pin 142	I/O — Bidirectional user I/O pin
Pin 143	I/O — Bidirectional user I/O pin
Pin 144	GND — Ground reference
Pin 145	I/O — Bidirectional user I/O pin
Pin 146	I/O — Bidirectional user I/O pin
Pin 147	I/O — Bidirectional user I/O pin
Pin 148	VCC — +5 V supply
Pin 149	I/O — Bidirectional user I/O pin
Pin 150	I/O — Bidirectional user I/O pin
Pin 151	I/O — Bidirectional user I/O pin
Pin 152	GND — Ground reference
Pin 153	I/O — Bidirectional user I/O pin
Pin 154	I/O — Bidirectional user I/O pin
Pin 155	I/O — Bidirectional user I/O pin
Pin 156	VCC — +5 V supply for I/O bank 10
Pin 157	I/O — Bidirectional user I/O pin
Pin 158	I/O — Bidirectional user I/O pin
Pin 159	I/O — Bidirectional user I/O pin
Pin 160	GND — Ground reference
Pin 161	I/O — Bidirectional user I/O pin
Pin 162	I/O — Bidirectional user I/O pin
Pin 163	I/O — Bidirectional user I/O pin
Pin 164	VCC — +5 V supply
Pin 165	I/O — Bidirectional user I/O pin
Pin 166	I/O — Bidirectional user I/O pin
Pin 167	I/O — Bidirectional user I/O pin
Pin 168	GND — Ground reference
Pin 169	I/O — Bidirectional user I/O pin
Pin 170	I/O — Bidirectional user I/O pin
Pin 171	I/O — Bidirectional user I/O pin
Pin 172	VCC — +5 V supply for I/O bank 11
Pin 173	I/O — Bidirectional user I/O pin
Pin 174	I/O — Bidirectional user I/O pin
Pin 175	I/O — Bidirectional user I/O pin
Pin 176	GND — Ground reference
Pin 177	I/O — Bidirectional user I/O pin
Pin 178	I/O — Bidirectional user I/O pin
Pin 179	I/O — Bidirectional user I/O pin
Pin 180	VCC — +5 V supply
Pin 181	TDI — JTAG Test Data In (IEEE 1149.1)
Pin 182	TMS — JTAG Test Mode Select
Pin 183	TCK — JTAG Test Clock
Pin 184	GND — Ground reference
Pin 185	TDO — JTAG Test Data Out
Pin 186	I/O — Bidirectional user I/O pin
Pin 187	I/O — Bidirectional user I/O pin
Pin 188	I/O — Bidirectional user I/O pin
Pin 189	VCC — +5 V supply for I/O bank 12
Pin 190	I/O — Bidirectional user I/O pin
Pin 191	I/O — Bidirectional user I/O pin
Pin 192	I/O — Bidirectional user I/O pin
Pin 193	GND — Ground reference
Pin 194	I/O — Bidirectional user I/O pin
Pin 195	I/O — Bidirectional user I/O pin
Pin 196	I/O — Bidirectional user I/O pin
Pin 197	VCC — +5 V supply
Pin 198	I/O — Bidirectional user I/O pin
Pin 199	I/O — Bidirectional user I/O pin
Pin 200	I/O — Bidirectional user I/O pin
Pin 201	GND — Ground reference
Pin 202	I/O — Bidirectional user I/O pin
Pin 203	I/O — Bidirectional user I/O pin
Pin 204	I/O — Bidirectional user I/O pin
Pin 205	VCC — +5 V supply for I/O bank 13
Pin 206	I/O — Bidirectional user I/O pin
Pin 207	I/O — Bidirectional user I/O pin
Pin 208	I/O — Bidirectional user I/O pin

Safe Operating Area (SOA) & Thermal Characteristics

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPM9560SRC208-7 is suitable for 6 applications: Processor-to-Peripheral Bus Glue Logic, Address Decoding and Wait-State Generation, Telecom Backplane Multiplexing, High-Speed State Machine Replacement, Industrial Controller Consolidation, Legacy System Sustainment / Obsolescence Mitigation.

🏭

Processor-to-Peripheral Bus Glue Logic

The EPM9560SRC208-7's 560 macrocells and 7 ns pin-to-pin delay make it ideal for replacing dozens of 74LS/74F glue-logic packages between a 32-bit microcontroller and its peripheral bus. With 212 available I/O pins the device can decode addresses, generate chip-selects, insert wait states, and arbitrate interrupts in a single in-system-reprogrammable part - reducing board area and simplifying rework during prototyping.

Recommended

EPM9560SRC208-10 (Pin-compatible 10 ns speed-grade for cost-reduced builds) EPM9480RC208-15 · Intel

🖥️

Address Decoding and Wait-State Generation

The 7 ns tPD of the EPM9560SRC208-7 is fast enough to perform synchronous address decoding on 50 MHz 16/32-bit microprocessor buses without inserting wait states on the first access. Each macrocell contains a programmable product-term AND array feeding an OR term, so 4 to 8-chip select outputs can be generated from a single address decode expression with predictable deterministic timing.

Recommended

EPM9560SRC208-15 (Pin-compatible 15 ns grade for slower bus architectures) EPM9560RI208-20 · Intel

🌐

Telecom Backplane Multiplexing

The MAX 9000 architecture's 212 I/Os allow the EPM9560SRC208-7 to mux and demux multiple low-speed telecom data streams (E1/T1 framing, HDLC channels, alarm/status lines) onto a single high-speed backplane bus. Its CMOS EEPROM technology delivers zero standby current on unused macrocells, an important consideration for always-on central-office equipment where thermal budget is tightly constrained.

Recommended

EPM9560RC208-7 · Altera EPM9560SRC208-20 (Slower speed-grade drop-in for cost-sensitive multiplexing)

⚙️

High-Speed State Machine Replacement

With 560 macrocells and a 7 ns tPD, the EPM9560SRC208-7 can replace dense discrete state-machine designs built from dozens of PALs and MSI logic. Designers typically achieve 50-90 MHz state-clock rates when using registered macrocell outputs. The JTAG (IEEE 1149.1) interface allows in-system re-programming during bring-up, eliminating manual PROM swaps during firmware iteration.

Recommended

EPM9560SRC208-10 (Pin-compatible 10 ns grade for relaxed timing budgets) EPM9320RC208-20 · Altera

🏭

Industrial Controller Consolidation

The EPM9560SRC208-7's 12,000 usable gates and 16 LABs let designers consolidate 20-30 discrete SSI/MSI logic packages into one programmable device on PLC and motion-controller boards. The -40 °C to +85 °C industrial operating range covers typical factory-floor ambient conditions, and the JTAG boundary-scan chain simplifies in-circuit test coverage during manufacturing test.

Recommended

EPM9560RI208-20N · Intel EPM9560SRC208-15 (Lower-speed-grade drop-in for relaxed timing)

✈️

Legacy System Sustainment / Obsolescence Mitigation

Because the EPM9560SRC208-7 is officially NRND (Not Recommended for New Designs), the device is often specified to sustain legacy industrial, military, and aerospace systems that must continue in production for 10+ years. Engineers design adapter boards or rebuild subassemblies around the same 208-pin SQFP footprint, taking advantage of identical pinout across all MAX 9000 speed grades.

Recommended

EPM9560SRC208-10 (Pin-compatible 10 ns speed grade with broader availability) EPM9560RC208-15 · Altera

Recommended Products Summary

EPM9560SRC208-10 Pin-compatible 10 ns speed-grade for cost-reduced builds Used in: Processor-to-Peripheral Bus Glue Logic, High-Speed State Machine Replacement, Legacy System Sustainment / Obsolescence Mitigation EPM9480RC208-15 Intel Used in: Processor-to-Peripheral Bus Glue Logic EPM9560SRC208-15 Pin-compatible 15 ns grade for slower bus architectures Used in: Address Decoding and Wait-State Generation, Industrial Controller Consolidation EPM9560RI208-20 Intel Used in: Address Decoding and Wait-State Generation EPM9560RC208-7 Altera Used in: Telecom Backplane Multiplexing EPM9560SRC208-20 Slower speed-grade drop-in for cost-sensitive multiplexing Used in: Telecom Backplane Multiplexing EPM9320RC208-20 Altera Used in: High-Speed State Machine Replacement EPM9560RI208-20N Intel Used in: Industrial Controller Consolidation EPM9560RC208-15 Altera Used in: Legacy System Sustainment / Obsolescence Mitigation

What is the EPM9560SRC208-7 and how many gates does it provide?

The EPM9560SRC208-7 is a high-density EPLD from Altera's MAX 9000 family that provides 12,000 usable gates and 560 macrocells in a 208-pin SQFP package. It is built on CMOS EEPROM technology and supports in-system programming via the IEEE Std 1149.1 JTAG interface. Source: Altera MAX 9000 family datasheet.

What is the pin-to-pin logic delay (tPD) of the EPM9560SRC208-7?

The 'SRC208-7' speed grade specifies a 7.0 ns pin-to-pin logic delay across the interconnect and macrocell chain. This makes the part suitable for glue-logic, address decoding, and synchronous state-machine replacement where the critical path is on the order of 50–140 MHz. Faster -10 and -15 variants are also offered in the same family.

How many I/O pins does the EPM9560SRC208-7 have?

The EPM9560 device provides up to 212 user I/O pins across the family; the SRC208-7 package exposes 208 pads with the remaining 4 reserved as power/ground or dedicated inputs (CLK1, CLK2, OE1, OE2, CLR). All I/O pins are bidirectional and programmable as input, output, or tri-state per macrocell configuration.

What is the difference between EPM9560SRC208-7 and EPM9560RC208-7?

The 'SRC' suffix denotes the 208-pin SQFP surface-mount package, while the 'RC' suffix denotes a 208-pin RQFP (ceramic/quad) variant of the same die. Both share the 7 ns speed grade and identical functional pinout. For new surface-mount designs the SRC is preferred; the RC is typically used in MIL-spec or extended-temperature programs.

Where to buy EPM9560SRC208-7 online?

The EPM9560SRC208-7 is widely listed by authorized Altera/Intel distributors and independent stock houses including VEKEMO, MFMIC, HKInventory, and Alibaba One-Stop BOM services (per verified web results). As of 2026-09-13 stock is fragmentary and lead times vary from immediate (1 pc) to 4–8 weeks for volume orders due to mature-lifecycle status.

What is the price of EPM9560SRC208-7?

As of 2026-09-13 the EPM9560SRC208-7 typically prices from approximately $70 to $95 per unit in single-piece quantities through authorized channels; volume pricing (1,000+) falls to roughly $45–$55 per unit. Pricing on the secondary market is volatile and depends on date-code, lot traceability, and country of origin.

What is the lead time for EPM9560SRC208-7?

As of 2026-09-13 lead time for the EPM9560SRC208-7 ranges from same-day for sub-100-piece orders at independent distributors to 4–8 weeks for franchise-channel volumes. Because the part is mature (NRND), engineers should request a formal quote and confirm factory stock before placing production orders.

Is EPM9560SRC208-7 in stock anywhere?

As of 2026-09-13 the EPM9560SRC208-7 is shown as available in limited quantities by independent distributors listed in the verified web data (VEKEMO, MFMIC, HKInventory, Alibaba). However, the part is officially NRND (Not Recommended for New Designs) by Altera/Intel, so supply is fragmentary and prices fluctuate significantly with market conditions.

EPM9560SRC208-7 vs EPM9480RC208-15 - which is better for high-density industrial control?

Both belong to the MAX 9000 family and share the 208-pin package footprint, but the EPM9560SRC208-7 provides 12,000 gates and 560 macrocells while the EPM9480RC208-15 offers 8,000 gates and 480 macrocells. Choose EPM9560SRC208-7 when you need maximum logic density at 7 ns timing; choose EPM9480RC208-15 when slightly slower 15 ns timing is acceptable and lower per-unit cost matters.

When should I choose EPM9560SRC208-7 over EPM9320RC208-20?

Choose EPM9560SRC208-7 when you need 12,000 gates, 560 macrocells, and a 7 ns pin-to-pin delay in a 208-pin package. Choose EPM9320RC208-20 when 6,000 gates and 320 macrocells at 20 ns are sufficient and you want a lower-cost part from the same MAX 9000 family. Both share identical JTAG programming flow and toolchain support.

What is the best drop-in replacement for EPM9560SRC208-7?

Drop-in package-compatible replacements within the MAX 9000 family include EPM9560SRC208-10 (10 ns speed grade, same SQFP-208 footprint), EPM9560SRC208-15 (15 ns, same footprint), and EPM9560SRC208-20 (20 ns). All four parts share identical pinout and JTAG chain, so a speed-grade swap is the safest drop-in change.

Hey Google, what can replace EPM9560SRC208-7?

Within the MAX 9000 family the EPM9560SRC208-10, -15, and -20 speed grades are the only pin-to-pin-compatible drop-in replacements for the -7 part - all share the 208-pin SQFP footprint and identical JTAG chain. For modern designs engineers typically migrate to Altera MAX II (EPM240, EPM570, EPM1270) or MAX V CPLDs in TQFP-100/144 packages, which requires PCB rework.

Where to download EPM9560SRC208-7 datasheet PDF?

The MAX 9000 family datasheet (which covers EPM9560SRC208-7) is available as a 182-page Altera PDF on alldatasheet.com at the URL listed in our data sources, and also as a 46-page family datasheet on datasheet4u.com. Both PDFs describe pinout, AC/DC specs, JTAG programming, and the MAX+PLUS II / Quartus design flow for this mature device family.

Where to find EPM9560SRC208-7 pinout and package dimensions?

The 208-pin SQFP pinout, mechanical dimensions, and recommended land pattern are documented in the Altera MAX 9000 family datasheet (Section - Package Information, referenced on alldatasheet.com). The SRC package is a surface-mount Quad Flat Pack with body width of approximately 30 mm and 0.5 mm pitch; pin 1 is marked by a dot on the top surface.

What are the key specifications of EPM9560SRC208-7 that engineers should know?

Key specifications: 12,000 usable gates, 560 macrocells across 16 LABs, 212 max I/O pins, 7 ns pin-to-pin delay, single 5 V supply, IEEE 1149.1 JTAG in-system programming, and -40 °C to +85 °C industrial operating range. The part is housed in a 208-pin SQFP surface-mount package and is now in NRND (Not Recommended for New Designs) lifecycle status.

Engineering reference data for EPM9560SRC208-7 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPM9560SRC208-7 when you need the maximum logic density (12,000 gates / 560 macrocells) and the fastest 7 ns pin-to-pin delay available in the MAX 9000 family, in a 208-pin SQFP surface-mount package. It is the right choice for 32-bit address decoding, high-speed state machines, and bus-interface consolidation in industrial or telecom equipment. For cost-sensitive or slower designs consider the same-die EPM9560SRC208-10 (10 ns) or EPM9560SRC208-15 (15 ns), which are pin-compatible drop-in alternatives with broader availability on the secondary market. The EPM9560RC208-7 RQFP ceramic variant should be selected only when MIL-spec or extended-temperature programs require a ceramic package.

Comparison with Alternatives

Parameter	This Product	EPM9560SRC208-10	EPM9560SRC208-15	EPM9560SRC208-20	EPM9560RC208-10	EPM9560RC208-7
Brand	Altera	Altera	Altera	Altera	Altera	Altera
Package	208-pin SQFP	208-pin SQFP - same	208-pin SQFP - same	208-pin SQFP - same	208-pin RQFP - footprint-compatible	208-pin RQFP - footprint-compatible
Usable Gates	12,000	12,000	12,000	12,000	12,000	12,000
Macrocells	560	560	560	560	560	560
Pin-to-Pin Delay (tPD)	7 ns	10 ns	15 ns	20 ns	10 ns	7 ns
Maximum I/O Pins	212	212	212	212	212	212
Supply Voltage	5 V	5 V	5 V	5 V	5 V	5 V
JTAG (IEEE 1149.1) Support	Yes (ISP + boundary-scan)	Yes	Yes	Yes	Yes	Yes
Lifecycle Status	NRND	NRND	NRND	NRND	NRND	NRND

Key Differentiators

Highest density in the MAX 9000 family with the fastest 7 ns speed grade (vs EPM9560SRC208-10)
Surface-mount SQFP package optimized for high-volume SMT assembly (vs EPM9560RC208-7)
Pin-compatible with all 208-pin SQFP MAX 9000 family members (vs EPM9320RC208-20)

Design Notes

The EPM9560SRC208-7 operates from a single 5 V supply and draws Icc dependent on switching activity. Decouple every VCC pin with a 0.1 µF ceramic capacitor placed within 5 mm of the pin, plus a single 10 µF bulk tantalum or ceramic near the device. Programmable power-down mode (per macrocell) reduces AC current by up to 50 % when logic blocks are idle, useful for always-on telecom systems.

Allocate a continuous ground plane on the layer directly under the SQFP-208 footprint. The 208-pin SQFP has a 0.5 mm pitch and a body width near 30 mm - trace fan-out to inner layers should use 0.15 mm / 6 mil traces. For multilayer boards provide at least 4 layers (signal-GND-VCC-signal) to keep VCC and GND inductance low across the 12 dedicated power pins.

Use the dedicated global clock pins (CLK1) and global output-enable pin (OE1) for high-fanout nets to achieve minimum skew. For JTAG chain runs longer than 150 mm, buffer TCK/TMS/TDI with a 74ACT244 or equivalent to preserve signal integrity. The IEEE 1149.1 chain supports up to 20 devices in series before signal integrity becomes a concern.

Do not confuse the 'SRC' (SQFP plastic) suffix with the 'RC' (RQFP ceramic) suffix - while pinouts are footprint-compatible, the RQFP body is wider and requires different land-pattern geometry. Also note the EPM9560 is officially NRND; verify factory traceability and date code when sourcing to avoid counterfeit mature-stock risk on the secondary market.

Compliance Information

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Lead Free

Unknown

Halogen Free

Unknown

Conflict Minerals

Unknown

Compliance status not explicitly stated in the mature MAX 9000 datasheet. The part is NRND; one Alibaba listing indicates ROHS3 compliance for current factory stock, but this should be verified per specific lot. AEC-Q100 not applicable for legacy programmable-logic devices of this generation.

Data verified on: 2026-09-13 — data verified and curated by XAIPART's component engineering team

Sources: Manufacturer_Datasheet, Manufacturer_Datasheet, Distributor, Distributor, Distributor, Distributor, Distributor, Manufacturer_Datasheet

Related Components & Terms

Altera Intel (Altera parent) EPM9560SRC208-7 EPM9560 EPM9560SRC208-10 EPM9560RC208-7 EPM9320RC208-20 MAX 9000 EPLD Erasable Programmable Logic Device macrocell Logic Array Block (LAB) CMOS EEPROM IEEE Std 1149.1 JTAG SQFP RQFP surface-mount 5 V supply industrial temperature range glue logic address decoding bus interface in-system programming (ISP)