EPM9560WC208-15 vs EPM9560WC208-20C Comparison
Detailed side-by-side comparison of EPM9560WC208-15 by Altera and EPM9560WC208-20C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-15 | EPM9560WC208-20C |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | — |
| Technology | CMOS | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Flip-Flops | 772 | — |
| User I/O Pins (max) | 149 | — |
| Maximum Clock Frequency | 117.6 MHz | [DATA_NEEDED: fMAX value not in verified data] |
| Propagation Delay (tPD) | 16.6 ns | 20 ns |
| Speed Grade | -15 | — |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Mounting Type | Surface Mount | Surface Mount (Ceramic QFP) |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | JTAG BST (in-system programmable) |
| RoHS Status | RoHS3 Compliant (per third-party listings) | ROHS3 Compliant (per fpgalink listing) |
| Device Family | — | MAX 9000 (EE PLD) |
| Series | — | EPM9560 |
| User I/O Pins | — | 149 |
| Process Technology | — | CMOS, Electrically Erasable |
| Supply Voltage | — | 3.3 V or 5 V (configurable I/O) |
| Pin Count | — | 208 |
| Operating Temperature Grade | — | Commercial (C suffix) |
| Moisture Sensitivity Level | — | MSL 3 (168 Hours) |