EPM9560WC208-20C vs EPM9560WC208-15 Comparison
Detailed side-by-side comparison of EPM9560WC208-20C by Altera and EPM9560WC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-20C | EPM9560WC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 9000 (EE PLD) | — |
| Series | EPM9560 | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 20 ns | 16.6 ns |
| Maximum Clock Frequency | [DATA_NEEDED: fMAX value not in verified data] | 117.6 MHz |
| Process Technology | CMOS, Electrically Erasable | — |
| Supply Voltage | 3.3 V or 5 V (configurable I/O) | — |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Pin Count | 208 | — |
| Programming Interface | JTAG BST (in-system programmable) | JTAG (IEEE 1149.1 boundary scan) |
| Operating Temperature Grade | Commercial (C suffix) | — |
| Mounting Type | Surface Mount (Ceramic QFP) | Surface Mount |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | RoHS3 Compliant (per third-party listings) |
| Moisture Sensitivity Level | MSL 3 (168 Hours) | — |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD (Electrically Erasable Programmable Logic Device) |
| Technology | — | CMOS |
| Flip-Flops | — | 772 |
| User I/O Pins (max) | — | 149 |
| Speed Grade | — | -15 |
| Supply Voltage - I/O | — | 3.3 V or 5.0 V (configurable) |
| Terminal Pitch | — | 0.50 mm |