EPM9560WI208-20 vs EPM9560WC208-15 Comparison

Detailed side-by-side comparison of EPM9560WI208-20 by Intel and EPM9560WC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560WI208-20

EPM9560WI208-20 - 560-Cell CPLD, 23.6ns, CQFP-208 | Intel / Altera

EPM9560WI208-20 Nrnd
Altera
EPM9560WC208-15

EPM9560WC208-15 - 560-Macrocell EE PLD, 117.6 MHz | Altera

EPM9560WC208-15 Obsolete

Specification Comparison

Parameter EPM9560WI208-20 EPM9560WC208-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $105.00 $105.00
Device Family MAX 9000 β€”
Device Type EE PLD / Complex Programmable Logic Device (CPLD) EE PLD (Electrically Erasable Programmable Logic Device)
Macrocells / Logic Cells 560 β€”
Logic Array Blocks (LABs) 16 35
Maximum User I/O Pins 212 β€”
Pin-to-Pin Propagation Delay (tPD) 23.6 ns β€”
Speed Grade -20 -15
Process Technology 0.35 micron CMOS EEPROM β€”
Programmability In-system via JTAG (IEEE 1149.1) β€”
Package Type CQFP-208 (Ceramic Quad Flat Pack) β€”
Terminal Form Gull Wing β€”
Number of Terminals 208 β€”
Package Code QFP β€”
Package Shape Square β€”
Operating Temperature Grade Industrial β€”
Mounting Type Surface Mount Surface Mount
Design Tools MAX+PLUS II, Quartus β€”
Compliance [DATA_NEEDED: RoHS status] β€”
Family β€” MAX 9000
Technology β€” CMOS
Macrocells β€” 560
Flip-Flops β€” 772
User I/O Pins (max) β€” 149
Maximum Clock Frequency β€” 117.6 MHz
Propagation Delay (tPD) β€” 16.6 ns
Supply Voltage - I/O β€” 3.3 V or 5.0 V (configurable)
Package β€” 208-pin CQFP (Ceramic Quad Flat Pack)
Terminal Pitch β€” 0.50 mm
Programming Interface β€” JTAG (IEEE 1149.1 boundary scan)
RoHS Status β€” RoHS3 Compliant (per third-party listings)

Datasheets & Resources

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