EPM9560WI208-20 - 560-Cell CPLD, 23.6ns, CQFP-208 | Intel / Altera
MPN: EPM9560WI208-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $140 | $14,000.00 |
| 500 | $120 | $60,000.00 |
| 1,000 | $105 | $105,000.00 |
Drop-in alternatives for EPM9560WI208-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560WC208-20
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EPM9560WC208-20C
✅ Drop-In✓ In Stock
$140 / Unit
View Datasheet →EPM9560WC208-15
✅ Drop-In✓ In Stock
$105 / Unit
View Datasheet →EPM9560WC208-15C
✅ Drop-In✓ In Stock
$178 / Unit
View Datasheet →EPM9560WC208
✅ Drop-In✓ In Stock
$125 / Unit
View Datasheet →EPM9560WI208-20 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Device Type | EE PLD / Complex Programmable Logic Device (CPLD) |
| Macrocells / Logic Cells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Pin-to-Pin Propagation Delay (tPD) | 23.6 ns |
| Speed Grade | -20 |
| Process Technology | 0.35 micron CMOS EEPROM |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Package Type | CQFP-208 (Ceramic Quad Flat Pack) |
| Terminal Form | Gull Wing |
| Number of Terminals | 208 |
| Package Code | QFP |
| Package Shape | Square |
| Operating Temperature Grade | Industrial |
| Mounting Type | Surface Mount |
| Design Tools | MAX+PLUS II, Quartus |
EPM9560WI208-20 Pin Configuration
| Pin 1 | I/O — User I/O pin (function defined by user design) |
| Pin 2 | I/O — User I/O pin (function defined by user design) |
| Pin 3 | I/O — User I/O pin (function defined by user design) |
| Pin 4 | I/O — User I/O pin (function defined by user design) |
| Pin 5 | I/O — User I/O pin (function defined by user design) |
| Pin 6 | I/O — User I/O pin (function defined by user design) |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O pin (function defined by user design) |
| Pin 9 | I/O — User I/O pin (function defined by user design) |
| Pin 10 | I/O — User I/O pin (function defined by user design) |
| Pin 11 | I/O — User I/O pin (function defined by user design) |
| Pin 12 | I/O — User I/O pin (function defined by user design) |
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| Pin 15 | I/O — User I/O pin (function defined by user design) |
| Pin 16 | I/O — User I/O pin (function defined by user design) |
| Pin 17 | VCC — Supply voltage (5 V) |
| Pin 18 | I/O — User I/O pin (function defined by user design) |
| Pin 19 | I/O — User I/O pin (function defined by user design) |
| Pin 20 | I/O — User I/O pin (function defined by user design) |
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| Pin 27 | I/O — User I/O pin (function defined by user design) |
| Pin 28 | I/O — User I/O pin (function defined by user design) |
| Pin 29 | GND — Ground |
| Pin 30 | I/O — User I/O pin (function defined by user design) |
| Pin 31 | I/O — User I/O pin (function defined by user design) |
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| Pin 41 | I/O — User I/O pin (function defined by user design) |
| Pin 42 | I/O — User I/O pin (function defined by user design) |
| Pin 43 | VCC — Supply voltage (5 V) |
| Pin 44 | I/O — User I/O pin (function defined by user design) |
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| Pin 56 | I/O — User I/O pin (function defined by user design) |
| Pin 57 | GND — Ground |
| Pin 58 | I/O — User I/O pin (function defined by user design) |
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| Pin 70 | I/O — User I/O pin (function defined by user design) |
| Pin 71 | I/O — User I/O pin (function defined by user design) |
| Pin 72 | VCC — Supply voltage (5 V) |
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| Pin 84 | I/O — User I/O pin (function defined by user design) |
| Pin 85 | GND — Ground |
| Pin 86 | I/O — User I/O pin (function defined by user design) |
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| Pin 100 | I/O — User I/O pin (function defined by user design) |
| Pin 101 | VCC — Supply voltage (5 V) |
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| Pin 116 | I/O — User I/O pin (function defined by user design) |
| Pin 117 | I/O — User I/O pin (function defined by user design) |
| Pin 118 | GND — Ground |
| Pin 119 | I/O — User I/O pin (function defined by user design) |
| Pin 120 | I/O — User I/O pin (function defined by user design) |
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| Pin 208 | I/O — User I/O pin (function defined by user design) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560WI208-20 is suitable for 6 applications: Aerospace and Military Avionics, Industrial Process Control, Telecommunication Line Cards, Legacy Bus-Bridge and Address Decoding, Test and Measurement Instrumentation, Medical Diagnostic Imaging Systems.
Aerospace and Military Avionics
The EPM9560WI208-20 fits aerospace and military avionics by combining 560 macrocells of deterministic glue logic with a hermetic CQFP-208 ceramic package rated for industrial temperature. Designers use the 23.6ns tPD to implement MIL-STD-1553 bus bridges, ARINC 429 line receivers, and radar timing controllers where instant-on EEPROM configuration is required and plastic QFP parts are prohibited. The JTAG-based IEEE 1149.1 boundary scan enables board-level test on flight hardware.
Recommended
Industrial Process Control
The EPM9560WI208-20 supports industrial process control by providing 560 macrocells and 212 user I/Os for PLC backplane glue, motor-control state machines, and deterministic sensor-fusion timing. The 23.6ns propagation delay meets deterministic cycle-time budgets for safety interlocks, and the ceramic package tolerates wide temperature swings near drives and furnaces. JTAG in-system programming simplifies field reconfiguration when process recipes change.
Recommended
Telecommunication Line Cards
The EPM9560WI208-20 addresses telecom line-card requirements by delivering 560 macrocells for TDM bus arbitration, framer interfacing, and protocol bridging across E1/T1 and SONET/SDH tributaries. The 23.6ns timing supports deterministic cell delineation, while 212 user I/Os accommodate multi-port front ends without external buffers. Instant-on EEPROM behavior eliminates external boot PROMs and reduces bill of materials cost per slot.
Recommended
Legacy Bus-Bridge and Address Decoding
The EPM9560WI208-20 acts as a legacy bus-bridge and address decoder between microprocessors, DSPs, ASICs, and FPGAs. With 560 macrocells and 23.6ns tPD, it can replace multiple discrete PAL/GAL devices and discrete logic gates, shrinking board area and improving signal integrity. The 208-pin QFP exposes enough user I/Os for 32-bit data buses plus dedicated chip-select and wait-state generation outputs.
Recommended
Test and Measurement Instrumentation
The EPM9560WI208-20 enables test and measurement front ends where deterministic timing and high I/O count are mandatory. It generates precise trigger patterns, scan-chain muxing, and reference clock conditioning for oscilloscopes and protocol analyzers. The 23.6ns tPD allows 42 MHz operation in synchronous state machines, and JTAG boundary-scan supports in-fixture test access on dense probe cards.
Recommended
Medical Diagnostic Imaging Systems
The EPM9560WI208-20 supports medical imaging by providing deterministic timing for ultrasound beamformer sequencing, MRI gradient control, and CT detector multiplexing. The 560-cell capacity integrates multiple timing and channel-select functions previously requiring several discrete PLDs. The ceramic CQFP-208 package tolerates autoclave-style sterilization cycles in surgical imaging carts and provides long-term reliability required by IEC 60601-1 medical equipment standards.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560WI208-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560WC208-20 | EPM9560WC208-20C | EPM9560WC208-15 | EPM9560WC208-15C | EPM9560WC208 |
|---|---|---|---|---|---|---|
| Package | CQFP-208 (Ceramic QFP) | CQFP-208 - same | CQFP-208 - same | CQFP-208 - same | CQFP-208 - same | CQFP-208 - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 23.6 ns (-20 speed grade) | 23.6 ns (-20) | 23.6 ns (-20) | 15 ns (-15 speed grade) | 15 ns (-15 speed grade) | [DATA_NEEDED] |
| Temperature Grade | Industrial | Commercial | Commercial (lead-free C-suffix) | Commercial | Commercial (lead-free C-suffix) | [DATA_NEEDED] |
| Maximum User I/O | 212 | 212 | 212 | 212 | 212 | 212 |
| Process / Architecture | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Approx. Price (qty 1, USD, as of 2026-09-13) | 185.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Industrial temperature grade in ceramic CQFP-208 (vs EPM9560WC208-20C)
- Highest-density MAX 9000 in 208-pin footprint (vs EPM9480RC208-20)
- Deterministic 23.6 ns tPD (vs EPM9560WC208-15)
Design Notes
The CQFP-208 ceramic package has gull-wing leads with larger pad geometry than a plastic QFP. Land pattern must follow the JEDEC MS-022 variation for ceramic QFP, with copper pads approximately 0.020 inch wider than the plastic variant to accommodate lead compliance. Inspect lead coplanarity during incoming QA; ceramic packages are more susceptible to lead warpage after thermal cycling.
Estimated: the MAX 9000 family draws approximately 200-400 mA from a 5 V supply at full I/O toggle, giving 1-2 W dissipation. In a ceramic QFP with typical theta_JA of 35-45 C/W, junction temperature rise above ambient stays below 90 C in normal industrial environments, but designers should derate by 10-15% in sealed aerospace enclosures without forced airflow.
Because the EPM9560WI208-20 drives 212 user I/Os at 23.6 ns edge rates, use series termination (22-33 ohm) on clock and high-fanout outputs to limit ringing on long PCB traces. Place VCC and GND pins with at least one decoupling cap pair (0.1 uF + 10 uF) within 5 mm of each supply pin to suppress SSO-induced ground bounce.
Do not assume the EPM9560WI208-20 is RoHS compliant without checking the manufacturer's material declaration; the ceramic CQFP historically used lead-bearing terminations. For new designs targeting RoHS, prefer the C-suffix variants (EPM9560WC208-20C, EPM9560WC208-15C) which carry lead-free finishes.
When laying out JTAG programming signals (TCK, TMS, TDI, TDO, TRST), keep the chain under 6 inches total to avoid IEEE 1149.1 timing violations. Provide a 10 kohm pull-up on TCK and TMS to keep the TAP controller in a benign state during board power-up before the CPLD is configured.
Compliance Information
Compliance values not explicitly stated in available distributor listings. The ceramic CQFP-208 package historically used lead-bearing terminations; the -WI- variant is not marked with a C-suffix and should be assumed non-RoHS until verified by manufacturer declaration.
