LFE2-20E-5F484C vs LFE2-6E-5F256I Comparison
Detailed side-by-side comparison of LFE2-20E-5F484C by Lattice Semiconductor and LFE2-6E-5F256I by Lattice Semiconductor. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | LFE2-20E-5F484C | LFE2-6E-5F256I |
|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Unknown | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Type | ECP2 Field Programmable Gate Array (FPGA) | ECP2 Field Programmable Gate Array (FPGA) |
| Logic Cell Density | 21K LUTs | — |
| Input/Output Count | 331 I/O | — |
| Core Supply Voltage | 1.2 V | — |
| Speed Grade | -5 | -5 |
| DSP Capability | DSP | — |
| Package | 484-BBGA | 256-ball Fine Pitch Ball Grid Array |
| Package Type | BGA | — |
| Terminal Count | 484 balls | 256 balls |
| Mounting Type | Surface Mount | Surface mount |
| Programmable Device | Yes | — |
| FPGA Family | LatticeECP2 | — |
| Logic Technology | 90 nm CMOS | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| Maximum Clock Frequency | [DATA_NEEDED: maximum clock frequency] | — |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| Logic Cells | — | 6,000 cells |
| User I/O | — | 190 I/O |
| Configuration Bits | — | 56,320 bits |
| Core Supply | — | 1.2 V |
| Temperature Grade | — | Industrial |
| Package Abbreviation | — | FPBGA-256 |
| Package Dimensions | — | 17 mm x 17 mm |
| Package Shape | — | Square |
| Terminal Type | — | Ball |
| Lead-Free Status | — | Lead free |
| Programmable Logic Type | — | FPGA |
| DSP Support | — | Advanced DSP blocks supported by the LatticeECP2/M family |
| SERDES Support | — | High-speed SERDES supported by the LatticeECP2M family |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification status] |