LFE2-6E-6FN256I vs LFE2-6E-5F256I Comparison
Detailed side-by-side comparison of LFE2-6E-6FN256I by Lattice Semiconductor and LFE2-6E-5F256I by Lattice Semiconductor. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Lattice Semiconductor
LFE2-6E-6FN256I - 6K LUT FPGA, 190 I/O, 256-BGA | Lattice
LFE2-6E-6FN256I ✓ ActiveSpecification Comparison
| Parameter | LFE2-6E-6FN256I | LFE2-6E-5F256I |
|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Device Type | ECP2 Field Programmable Gate Array (FPGA) | ECP2 Field Programmable Gate Array (FPGA) |
| Logic Cells | 6,000 cells | 6,000 cells |
| Logic Blocks | 750 LABs | — |
| Embedded RAM | 56,320 bits (67 KB) | — |
| User I/O | 190 I/O | 190 I/O |
| Maximum Frequency | 357 MHz | — |
| Core Supply Voltage | 1.14 V to 1.26 V | — |
| Nominal Core Voltage | 1.2 V | — |
| Process Technology | 90 nm | — |
| Operating Temperature | -40°C to +100°C | — |
| Temperature Grade | Industrial | Industrial |
| Package | 256-ball FBGA, 17 mm × 17 mm | 256-ball Fine Pitch Ball Grid Array |
| Package Code | FPBGA-256 | — |
| Mounting Type | Surface Mount | Surface mount |
| Terminal Type | Ball | Ball |
| Number of Terminals | 256 balls | — |
| Package Shape | Square | Square |
| Lead-Free Status | Lead free | Lead free |
| Standard Packaging | Tray | — |
| Standard Quantity | 90 units | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH compliance status] | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification status] | [DATA_NEEDED: AEC-Q100 qualification status] |
| Configuration Bits | — | 56,320 bits |
| Core Supply | — | 1.2 V |
| Speed Grade | — | -5 |
| Package Abbreviation | — | FPBGA-256 |
| Package Dimensions | — | 17 mm x 17 mm |
| Terminal Count | — | 256 balls |
| Programmable Logic Type | — | FPGA |
| DSP Support | — | Advanced DSP blocks supported by the LatticeECP2/M family |
| SERDES Support | — | High-speed SERDES supported by the LatticeECP2M family |