MPC8548PXAUJB vs MPC8536EAVTAQG Comparison

Detailed side-by-side comparison of MPC8548PXAUJB by NXP Semiconductors and MPC8536EAVTAQG by NXP Semiconductors. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

NXP Semiconductors
MPC8548PXAUJB MPC8548PXAUJB - PowerPC e500 MPU 1.333GHz 783-FCBGA | NXP

MPC8548PXAUJB - PowerPC e500 MPU 1.333GHz 783-FCBGA | NXP

MPC8548PXAUJB ✓ Active
NXP Semiconductors
MPC8536EAVTAQG MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale

MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale

MPC8536EAVTAQG Nrnd

Specification Comparison

Parameter MPC8548PXAUJB MPC8536EAVTAQG
Brand NXP Semiconductors NXP Semiconductors
Category Microcontrollers Microcontrollers
Lifecycle Status Active NRND
Stock Status In Stock In Stock
Unit Price (USD) $121.75 $218.75
Manufacturer NXP Semiconductors (formerly Freescale) —
Series PowerQUICC III / MPC85xx —
Core Architecture PowerPC e500 (32-bit) —
Number of Cores 1 1
Maximum Core Frequency 1.333 GHz —
Package 783-FCBGA (29x29 mm) 783-FCPBGA (29x29 mm)
Mounting Type Surface Mount Surface Mount (BGA)
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
L1 Cache 32 KB instruction + 32 KB data —
L2 Cache [DATA_NEEDED: L2 cache size] —
Memory Controller DDR2 SDRAM, up to [DATA_NEEDED: max memory] —
Ethernet 4x Gigabit Ethernet (SGMII) —
PCI Express [DATA_NEEDED: PCIe lane count] —
RapidIO Yes (serial RapidIO) —
QUICC Engine Yes (protocol offload subsystem) —
RoHS Status Compliant (per NXP product page) [DATA_NEEDED: RoHS compliance]
Lead-Free Yes —
Processor Series — MPC85xx (PowerQUICC III)
Core — PowerPC e500, 32-bit
Maximum Clock Frequency — 1.0 GHz
Data Bus Width — 32 bit
Encryption Support — Yes ('E' suffix indicates encryption-enabled silicon)
Supply Voltage — [DATA_NEEDED: core/IO supply voltage]
Integrated Peripherals — QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express
Instruction Set Architecture — Power Architecture (Book-E)
On-chip Cache — [DATA_NEEDED: L1/L2 cache configuration]
MSL Level — [DATA_NEEDED: MSL rating]

Datasheets & Resources

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