MPC8548PXAUJB vs MPC8536EAVTAQG Comparación
Comparación detallada lado a lado de MPC8548PXAUJB por NXP Semiconductors y MPC8536EAVTAQG por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale
MPC8536EAVTAQG NrndComparación de especificaciones
| Parámetro | MPC8548PXAUJB | MPC8536EAVTAQG |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $121,75 | $218,75 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | PowerQUICC III / MPC85xx | — |
| Core Architecture | PowerPC e500 (32-bit) | — |
| Number of Cores | 1 | 1 |
| Maximum Core Frequency | 1.333 GHz | — |
| Encapsulado | 783-FCBGA (29x29 mm) | 783-FCPBGA (29x29 mm) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| L1 Cache | 32 KB instruction + 32 KB data | — |
| L2 Cache | [DATA_NEEDED: L2 cache size] | — |
| Memory Controller | DDR2 SDRAM, up to [DATA_NEEDED: max memory] | — |
| Ethernet | 4x Gigabit Ethernet (SGMII) | — |
| PCI Express | [DATA_NEEDED: PCIe lane count] | — |
| RapidIO | Yes (serial RapidIO) | — |
| QUICC Engine | Yes (protocol offload subsystem) | — |
| Estado RoHS | Compliant (per NXP product page) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Processor Series | — | MPC85xx (PowerQUICC III) |
| Core | — | PowerPC e500, 32-bit |
| Frecuencia de reloj máxima | — | 1.0 GHz |
| Ancho del bus de datos | — | 32 bit |
| Encryption Support | — | Yes ('E' suffix indicates encryption-enabled silicon) |
| Tensión de alimentación | — | [DATA_NEEDED: core/IO supply voltage] |
| Integrated Peripherals | — | QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express |
| Instruction Set Architecture | — | Power Architecture (Book-E) |
| On-chip Cache | — | [DATA_NEEDED: L1/L2 cache configuration] |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |