XC3090L-125PC84C vs XC3090L-8PC84BKJ Comparison
Detailed side-by-side comparison of XC3090L-125PC84C by Xilinx and XC3090L-8PC84BKJ by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090L-125PC84C
XC3090L-125PC84C - 5K-Gate FPGA, 125MHz, 84-Pin PLCC | Xilinx
XC3090L-125PC84C ObsoleteXilinx
XC3090L-8PC84BKJ
XC3090L-8PC84BKJ - XC3000L 5V FPGA 84-Pin PLCC | AMD Xilinx
XC3090L-8PC84BKJ ObsoleteSpecification Comparison
| Parameter | XC3090L-125PC84C | XC3090L-8PC84BKJ |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $64.00 | $19.20 |
| Manufacturer | Xilinx | β |
| Series | XC3000L | β |
| Product Type | Field Programmable Gate Array (FPGA) | β |
| Logic Family | XC3000L Low-Voltage Logic Cell Array | β |
| Process Technology | CMOS, SRAM-based | 5 ns CMOS SRAM |
| Configurable Logic Blocks (CLBs) | 320 | β |
| Equivalent Gates | ~5,000 | β |
| Flip-Flops | 928 | β |
| Maximum Toggle Frequency | 125 MHz | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) | β |
| Operating Temperature | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] | 0C to +70C (commercial, C suffix) |
| Package | 84-pin PLCC (J-lead, package code QCCJ) | 84-pin PLCC (J-Lead), windowed ceramic (BKJ) |
| Terminal Form | J-BEND (J-lead) | β |
| Mounting Type | Surface Mount | Through-hole (PLCC socket) |
| Configuration Interface | Serial/parallel mode, JTAG (IEEE 1149.1) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | unknown - legacy windowed ceramic package |
| Family | β | XC3000L Low-Voltage Logic Cell Array |
| Logic Cells | β | 320 |
| Usable Gates | β | 6,000 |
| Configuration Memory | β | 64,160 bits |
| Maximum User I/O | β | 144 |
| Supply Voltage (Vcc) | β | 3.0 V to 3.6 V (low-voltage) |
| Speed Grade | β | -8 (approx. 70 MHz toggle) |
| Configuration Method | β | Serial/parallel SRAM, in-system reconfigurable |
| Boundary Scan | β | IEEE 1149.1 (JTAG) compliant |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Configuration Pins | β | M0, M1, M2 mode-select + DIN, DOUT, CCLK, INIT |