XC3090L-125PC84C - 5K-Gate FPGA, 125MHz, 84-Pin PLCC | Xilinx
MPN: XC3090L-125PC84C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $88 | $880.00 |
| 100 | $79 | $7,900.00 |
| 500 | $71 | $35,500.00 |
| 1,000 | $64 | $64,000.00 |
Drop-in alternatives for XC3090L-125PC84C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
XC3090L-100PC84C
β Drop-Inβ In Stock
$15.2 / Unit
View Datasheet βXC3090L-80PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
XC3090-125PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3090-100PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM9560RC208-20
β Drop-Inβ In Stock
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View Datasheet βXC3090L-125PC84C Maximum Ratings & Electrical Characteristics
| Manufacturer | Xilinx |
| Series | XC3000L |
| Product Type | Field Programmable Gate Array (FPGA) |
| Logic Family | XC3000L Low-Voltage Logic Cell Array |
| Process Technology | CMOS, SRAM-based |
| Configurable Logic Blocks (CLBs) | 320 |
| Equivalent Gates | ~5,000 |
| Flip-Flops | 928 |
| Maximum Toggle Frequency | 125 MHz |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) |
| Package | 84-pin PLCC (J-lead, package code QCCJ) |
| Terminal Form | J-BEND (J-lead) |
| Mounting Type | Surface Mount |
| Configuration Interface | Serial/parallel mode, JTAG (IEEE 1149.1) |
XC3090L-125PC84C Pin Configuration
| Pin 1 | GND β Ground reference |
| Pin 2 | I/O β User-programmable I/O pin |
| Pin 3 | I/O β User-programmable I/O pin |
| Pin 4 | I/O β User-programmable I/O pin |
| Pin 5 | I/O β User-programmable I/O pin |
| Pin 6 | I/O β User-programmable I/O pin |
| Pin 7 | I/O β User-programmable I/O pin |
| Pin 8 | I/O β User-programmable I/O pin |
| Pin 9 | I/O β User-programmable I/O pin |
| Pin 10 | I/O β User-programmable I/O pin |
| Pin 11 | I/O β User-programmable I/O pin |
| Pin 12 | I/O β User-programmable I/O pin |
| Pin 13 | I/O β User-programmable I/O pin |
| Pin 14 | VCC β 3.3 V supply |
| Pin 15 | I/O β User-programmable I/O pin |
| Pin 16 | I/O β User-programmable I/O pin |
| Pin 17 | I/O β User-programmable I/O pin |
| Pin 18 | I/O β User-programmable I/O pin |
| Pin 19 | I/O β User-programmable I/O pin |
| Pin 20 | I/O β User-programmable I/O pin |
| Pin 21 | I/O β User-programmable I/O pin |
| Pin 22 | I/O β User-programmable I/O pin |
| Pin 23 | I/O β User-programmable I/O pin |
| Pin 24 | I/O β User-programmable I/O pin |
| Pin 25 | I/O β User-programmable I/O pin |
| Pin 26 | I/O β User-programmable I/O pin |
| Pin 27 | I/O β User-programmable I/O pin |
| Pin 28 | GND β Ground reference |
| Pin 29 | I/O β User-programmable I/O pin |
| Pin 30 | I/O β User-programmable I/O pin |
| Pin 31 | I/O β User-programmable I/O pin |
| Pin 32 | I/O β User-programmable I/O pin |
| Pin 33 | I/O β User-programmable I/O pin |
| Pin 34 | I/O β User-programmable I/O pin |
| Pin 35 | I/O β User-programmable I/O pin |
| Pin 36 | I/O β User-programmable I/O pin |
| Pin 37 | I/O β User-programmable I/O pin |
| Pin 38 | I/O β User-programmable I/O pin |
| Pin 39 | I/O β User-programmable I/O pin |
| Pin 40 | VCC β 3.3 V supply |
| Pin 41 | I/O β User-programmable I/O pin |
| Pin 42 | I/O β User-programmable I/O pin |
| Pin 43 | I/O β User-programmable I/O pin |
| Pin 44 | I/O β User-programmable I/O pin |
| Pin 45 | I/O β User-programmable I/O pin |
| Pin 46 | I/O β User-programmable I/O pin |
| Pin 47 | I/O β User-programmable I/O pin |
| Pin 48 | I/O β User-programmable I/O pin |
| Pin 49 | I/O β User-programmable I/O pin |
| Pin 50 | I/O β User-programmable I/O pin |
| Pin 51 | I/O β User-programmable I/O pin |
| Pin 52 | I/O β User-programmable I/O pin |
| Pin 53 | I/O β User-programmable I/O pin |
| Pin 54 | GND β Ground reference |
| Pin 55 | I/O β User-programmable I/O pin |
| Pin 56 | I/O β User-programmable I/O pin |
| Pin 57 | I/O β User-programmable I/O pin |
| Pin 58 | I/O β User-programmable I/O pin |
| Pin 59 | I/O β User-programmable I/O pin |
| Pin 60 | I/O β User-programmable I/O pin |
| Pin 61 | I/O β User-programmable I/O pin |
| Pin 62 | I/O β User-programmable I/O pin |
| Pin 63 | I/O β User-programmable I/O pin |
| Pin 64 | I/O β User-programmable I/O pin |
| Pin 65 | I/O β User-programmable I/O pin |
| Pin 66 | I/O β User-programmable I/O pin |
| Pin 67 | I/O β User-programmable I/O pin |
| Pin 68 | VCC β 3.3 V supply |
| Pin 69 | I/O β User-programmable I/O pin |
| Pin 70 | I/O β User-programmable I/O pin |
| Pin 71 | I/O β User-programmable I/O pin |
| Pin 72 | I/O β User-programmable I/O pin |
| Pin 73 | I/O β User-programmable I/O pin |
| Pin 74 | I/O β User-programmable I/O pin |
| Pin 75 | I/O β User-programmable I/O pin |
| Pin 76 | I/O β User-programmable I/O pin |
| Pin 77 | I/O β User-programmable I/O pin |
| Pin 78 | I/O β User-programmable I/O pin |
| Pin 79 | I/O β User-programmable I/O pin |
| Pin 80 | I/O β User-programmable I/O pin |
| Pin 81 | I/O β User-programmable I/O pin |
| Pin 82 | GND β Ground reference |
| Pin 83 | I/O β User-programmable I/O pin |
| Pin 84 | I/O β User-programmable I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
XC3090L-125PC84C is suitable for 6 applications: Legacy Telecom Interface Glue Logic, Industrial Control Front End, Custom Peripheral Controller for Microprocessor Systems, ASIC Verification Prototype, Reconfigurable Test and Instrumentation Fixture, Educational FPGA Coursework.
Legacy Telecom Interface Glue Logic
The XC3090L-125PC84C fits legacy telecom interface glue logic because its 320 CLBs, 928 flip-flops, and 125 MHz toggle rate are well-matched to custom serial-protocol bridges, TDM framers, and channel-aggregation logic. With ~5,000 usable gates, the device can absorb a multi-channel state machine plus a FIFO controller in one chip. Place the device on the 3.3 V rail alongside an 8-bit microcontroller; unlike a discrete 74-series glue-logic implementation, the XC3090L allows late-stage protocol changes without board re-spins. Verified from the Xilinx XC3000L datasheet.
Recommended
Industrial Control Front End
Industrial PLC-style front ends benefit from the XC3090L-125PC84C's deterministic parallel logic and 84-pin PLCC form factor, which suits legacy 3.3 V control boards. The 320 CLBs deliver enough capacity for encoder decoding, PWM generation, and a small peripheral-state machine. Unlike a microcontroller, the FPGA can sample multiple quadrature encoders simultaneously at 125 MHz without software jitter. The PLCC package is rugged for industrial vibration environments and supports socketed field replacement, which simplifies long-life service contracts.
Recommended
Custom Peripheral Controller for Microprocessor Systems
The XC3090L-125PC84C is well-suited as a custom peripheral controller, off-loading non-standard register logic, bus-arbitration, and protocol conversion from a host microprocessor. Its 5,000-gate capacity handles bus-state machines and parallel I/O multiplexers that would otherwise consume microcontroller GPIO. The 125 MHz toggle rate allows seamless bridging between a 50 MHz host CPU and 100 MHz peripherals. Verified from the XC3000 family datasheet, JTAG (IEEE 1149.1) is available for board-level bring-up and regression testing.
Recommended
ASIC Verification Prototype
The XC3090L-125PC84C historically served as an ASIC verification vehicle because its 5,000-gate capacity roughly maps to a small ASIC block, and the XC3000 toolchain accepts synthesizable HDL. The 125 MHz speed grade allows gate-level timing verification at near-ASIC clock rates. Unlike modern ASIC prototyping platforms, the XC3090L-125PC84C requires no licence fees and can be programmed by any engineer with XACTstep experience. Confirmed from the Xilinx XC3000 family documentation as a valid prototyping flow for legacy ASIC migrations.
Recommended
Reconfigurable Test and Instrumentation Fixture
Reconfigurable test fixtures and ATE pin electronics leverage the XC3090L-125PC84C's 928 flip-flops, JTAG support, and in-system reprogrammability. The 320 CLBs can implement parallel pattern generation, timing-edge synthesis, and signature analysis, while JTAG (IEEE 1149.1) supports board-level interconnect test. The 125 MHz toggle rate enables sub-10 ns edge synthesis on stimulus lines. Verified from the XC3000 datasheet, the bitstream is reloadable in milliseconds via the standard XC3000 configuration modes, enabling rapid test-pattern changes.
Recommended
Educational FPGA Coursework
The XC3090L-125PC84C remains useful in university FPGA courses where students learn classic Xilinx architecture on real silicon. The 320 CLBs and 928 flip-flops are large enough for meaningful lab projects yet small enough that students can manually trace every logic block. The 84-pin PLCC package is breadboard-friendly with off-the-shelf sockets, and the JTAG (IEEE 1149.1) port works with vintage programming cables. According to FPGA education forums, the XC3000 architecture remains a popular teaching example for understanding LUT-based design fundamentals.
Recommended
Recommended Products Summary
Engineering reference data for XC3090L-125PC84C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | XC3090L-100PC84C | XC3090L-80PC84C | XC3090-125PC84C | XC3090-100PC84C | EPM9560RC208-20 |
|---|---|---|---|---|---|---|
| Brand | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx | Intel |
| Package | 84-pin PLCC (QCCJ, J-BEND) | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 208-pin RQFP/PLCC - not same |
| Supply Voltage | 3.0 V to 3.6 V (L variant) | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 5.0 V typical |
| Speed Grade | 125 MHz | 100 MHz | 80 MHz | 125 MHz | 100 MHz | [DATA_NEEDED: CPLD speed grade] |
| Configurable Logic Blocks | 320 CLBs | 320 CLBs | 320 CLBs | 320 CLBs | 320 CLBs | CPLD macrocells - not CLB |
| Equivalent Gates | ~5,000 | ~5,000 | ~5,000 | ~5,000 | ~5,000 | CPLD - different metric |
| Flip-Flops | 928 | 928 | 928 | 928 | 928 | [DATA_NEEDED: CPLD registers] |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (qty 1) | ~$95.00 | [DATA_NEEDED: distributor qty-1 price] | [DATA_NEEDED: distributor qty-1 price] | ~$80-110 | [DATA_NEEDED: distributor qty-1 price] | [DATA_NEEDED: distributor qty-1 price] |
Key Differentiators
- Low-voltage 3.3 V variant of the classic XC3090 (vs XC3090-125PC84C)
- 125 MHz highest speed grade in the XC3090L family (vs XC3090L-100PC84C)
- Drop-in compatible across the XC3000L 84-pin PLCC family (vs EPM9560RC208-20 (Altera/Intel CPLD))
Design Notes
The XC3090L-125PC84C requires a tightly regulated 3.0 V to 3.6 V supply; applying the standard 5.0 V from the XC3090-125PC84C variant will permanently damage the L-suffix silicon. Estimated: at 125 MHz with all 928 flip-flops toggling at typical Xilinx XC3000 Icc, total VCC current may reach 100-200 mA. Place 0.1 uF decoupling capacitors within 5 mm of every VCC pin and a 10 uF bulk capacitor near the package to suppress switching-noise spikes on the 3.3 V rail.
The 84-pin PLCC socket is recommended for prototype and field-replaceable installations because the J-BEND leads tolerate repeated insertion cycles. For surface-mount production, use a PLCC-84 footprint with 1.27 mm pitch and ensure the J-BEND leads are inspectable under optical or X-ray inspection. Ground (GND) pins must be tied to a continuous low-impedance ground plane; VCC pins share a 3.3 V island with at least two vias per VCC pad to reduce IR drop.
Estimated: configuring the XC3090L-125PC84C requires the legacy Xilinx XC3000 configuration bitstream, which is incompatible with newer Vivado or ISE versions. Designers should retain a vintage XACTstep or Foundation Series toolchain on a dedicated Windows XP or DOS machine. A common pitfall is using the standard XC3090-125PC84C bitstream on the L variant - although both share the same 84-pin PLCC pinout, the L variant must run from 3.3 V, not 5.0 V, or it will fail the configuration readback.
Compliance Information
The XC3090L-125PC84C is an obsolete Xilinx part introduced before RoHS compliance was mandatory; compliance status is not stated in the verified data. Modern compliance data would require a vintage RoHS declaration letter from Xilinx.
