XC9572-10PC44I vs XC9572-15PC44I Comparison
Detailed side-by-side comparison of XC9572-10PC44I by AMD and XC9572-15PC44I by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | XC9572-10PC44I | XC9572-15PC44I |
|---|---|---|
| Brand | AMD | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | End of Life |
| Device Type | Complex Programmable Logic Device (CPLD) | In-system programmable CPLD |
| Macrocell Count | 72 macrocells | 72 macrocells |
| Usable Gate Count | 1,600 gates | — |
| User I/O Count | 34 I/O | — |
| Function Block Count | 8 function blocks | — |
| Function Block Architecture | 8 blocks of 36V18 | — |
| Speed Grade | 10 ns | — |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Maximum System Clock Frequency | 66.7 MHz | — |
| Counter Frequency | Up to 125 MHz | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Nominal Supply Voltage | 5 V | — |
| Process Technology | 0.5 µm Advanced CMOS | — |
| Configuration Technology | 5 V Fast FLASH in-system programming | 5 V Fast FLASH |
| Programming Endurance | At least 10,000 program/erase cycles | — |
| Operating Temperature Range | -40°C to +85°C | — |
| Temperature Grade | Industrial | Industrial |
| Package | 44-pin PLCC | 44-LCC J-lead (PLCC), square |
| Mounting Type | Surface mount | — |
| Parallel Programming Support | Supported | — |
| RoHS Status | Non-compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | Contains lead | [DATA_NEEDED: lead-free status] |
| Programming Pinout | [DATA_NEEDED: complete 44-pin PLCC pin assignment] | — |
| Architecture | — | Advanced CMOS 5 V Fast FLASH |
| Propagation Delay | — | 15 ns speed grade |
| Family Pin-to-Pin Logic Delay | — | 5 ns |
| Family Maximum Counting Frequency | — | 125 MHz |
| I/O Line Count | — | 34 I/O |
| Maximum Supply Voltage | — | 5.5 V |
| Programming Support | — | In-system programming and parallel programming of multiple XC9500 devices |
| Package Code | — | QCCJ |
| Terminal Count | — | 44 terminals |
| Terminal Form | — | J-bend |
| Transient Pin Overshoot | — | Up to +7.0 V for less than 10 ns with forcing current limited to 200 mA |
| Transient Pin Undershoot | — | Down to -2.0 V for less than 10 ns with forcing current limited to 200 mA |
| Maximum DC Undershoot Below Ground | — | Limited to either 0.5 V or 10 mA, whichever is easier to achieve |
| External I/O Voltage Limit | — | May not exceed VCCINT by more than 4.0 V |
| REACH Status | — | [DATA_NEEDED: REACH compliance status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification status] |