10AS048K2F35E1HG vs 10AS048K1F35E1HG Vergleich
Detaillierter Direktvergleich von 10AS048K2F35E1HG von Intel und 10AS048K1F35E1HG von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10AS048K2F35E1HG | 10AS048K1F35E1HG |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2.650,00 | $3.850,00 |
| Product Family | Arria 10 SX SoC FPGA | — |
| Logic Elements | 480,000 | 480,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| DSP Blocks | 1,518 (variable-precision, IEEE 754 FP) | Variable-precision DSP blocks (per family) |
| Adaptive Logic Modules (ALMs) | 190,240 | — |
| Embedded Memory | [DATA_NEEDED: total M20K + MLAB bits] | — |
| Maximum User I/O Pins | 396 | — |
| Transceivers | [DATA_NEEDED: number of GX/GT channels and data rate] | Multi-gigabit serial transceivers, up to 17.4 Gbps (family) |
| Process Technology | TSMC 20 nm | 20 nm |
| Gehäuse | 1152-BBGA, FCBGA, 35 x 35 mm | 1152-ball FC-BGA (flip-chip), 35x35 mm |
| Betriebstemperatur | 0C to 100C (E1 = Enhanced, 0C to 100C) | Industrial / commercial per part number suffix |
| Speed Grade | K2 | — |
| Hard Memory Controllers | DDR3/DDR4 with ECC support | — |
| HPS Peripherals | USB 2.0 OTG, GbE, SD/SDIO/MMC, UART, SPI, I2C, CAN | Gigabit Ethernet, USB 2.0 OTG, SD/SDIO/MMC, SPI, I2C, UART, CAN |
| Security Features | AES, SHA, RSA, TrustZone, secure boot, anti-tamper | — |
| RoHS-Status | Compliant | Compliant |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Product Series | — | Arria 10 SX SoC FPGA |
| HPS Clock Speed | — | Up to 1.5 GHz |
| Memory Interfaces | — | DDR4, DDR3, LPDDR3, QDR IV (hard controllers) |
| On-chip RAM | — | M20K memory blocks + MLAB (per family) |
| Hard IP Blocks | — | PCIe Gen3 (hard), 10/40 GbE MAC, DDR controllers, partial reconfiguration |
| Configuration | — | FPGA fabric + HPS independent configuration, supports AS/PS/JTAG |
| REACH Status | — | [DATA_NEEDED: REACH compliance] |
| Design Software | — | Intel Quartus Prime (legacy: Altera Quartus II) |